526 lines
11 KiB
Plaintext
526 lines
11 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 Gateworks Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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key-user-pb {
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label = "user_pb";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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key-user-pb1x {
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label = "user_pb1x";
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linux,code = <BTN_1>;
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interrupt-parent = <&gsc>;
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interrupts = <0>;
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};
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key-erased {
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label = "key_erased";
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linux,code = <BTN_2>;
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interrupt-parent = <&gsc>;
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interrupts = <1>;
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};
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key-eeprom-wp {
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label = "eeprom_wp";
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linux,code = <BTN_3>;
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interrupt-parent = <&gsc>;
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interrupts = <2>;
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};
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key-tamper {
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label = "tamper";
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linux,code = <BTN_4>;
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interrupt-parent = <&gsc>;
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interrupts = <5>;
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};
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switch-hold {
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label = "switch_hold";
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linux,code = <BTN_5>;
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interrupt-parent = <&gsc>;
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interrupts = <7>;
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};
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};
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};
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&A53_0 {
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cpu-supply = <&buck3_reg>;
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};
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&A53_1 {
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cpu-supply = <&buck3_reg>;
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};
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&A53_2 {
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cpu-supply = <&buck3_reg>;
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};
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&A53_3 {
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cpu-supply = <&buck3_reg>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25000000 {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750000000 {
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opp-hz = /bits/ 64 <750000000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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pinctrl-0 = <&pinctrl_gsc>;
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interrupt-parent = <&gpio2>;
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interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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adc {
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compatible = "gw,gsc-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@6 {
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gw,mode = <0>;
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reg = <0x06>;
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label = "temp";
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};
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channel@8 {
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gw,mode = <1>;
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reg = <0x08>;
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label = "vdd_bat";
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};
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channel@16 {
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gw,mode = <4>;
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reg = <0x16>;
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label = "fan_tach";
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};
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channel@82 {
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gw,mode = <2>;
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reg = <0x82>;
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label = "vdd_vin";
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gw,voltage-divider-ohms = <22100 1000>;
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};
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channel@84 {
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gw,mode = <2>;
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reg = <0x84>;
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label = "vdd_adc1";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@86 {
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gw,mode = <2>;
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reg = <0x86>;
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label = "vdd_adc2";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@88 {
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gw,mode = <2>;
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reg = <0x88>;
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label = "vdd_dram";
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};
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channel@8c {
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gw,mode = <2>;
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reg = <0x8c>;
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label = "vdd_1p2";
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};
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channel@8e {
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gw,mode = <2>;
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reg = <0x8e>;
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label = "vdd_1p0";
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};
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channel@90 {
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gw,mode = <2>;
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reg = <0x90>;
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label = "vdd_2p5";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@92 {
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gw,mode = <2>;
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reg = <0x92>;
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label = "vdd_3p3";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@98 {
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gw,mode = <2>;
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reg = <0x98>;
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label = "vdd_0p95";
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};
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channel@9a {
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gw,mode = <2>;
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reg = <0x9a>;
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label = "vdd_1p8";
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};
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channel@a2 {
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gw,mode = <2>;
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reg = <0xa2>;
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label = "vdd_gsc";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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};
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fan-controller@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "gw,gsc-fan";
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reg = <0x0a>;
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};
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};
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gpio: gpio@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gsc>;
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interrupts = <4>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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rtc@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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pmic@69 {
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compatible = "mps,mp5416";
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reg = <0x69>;
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regulators {
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/* vdd_0p95: DRAM/GPU/VPU */
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buck1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1000000>;
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regulator-min-microamp = <3800000>;
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regulator-max-microamp = <6800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_soc */
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buck2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-min-microamp = <2200000>;
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regulator-max-microamp = <5200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_arm */
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buck3_reg: buck3 {
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regulator-name = "buck3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1000000>;
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regulator-min-microamp = <3800000>;
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regulator-max-microamp = <6800000>;
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regulator-always-on;
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};
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/* vdd_1p8 */
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buck4 {
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regulator-name = "buck4";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-min-microamp = <2200000>;
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regulator-max-microamp = <5200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* nvcc_snvs_1p8 */
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ldo1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_snvs_0p8 */
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ldo2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_0p9 */
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ldo3 {
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regulator-name = "ldo3";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_1p8 */
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ldo4 {
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regulator-name = "ldo4";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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eeprom@52 {
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compatible = "atmel,24c32";
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reg = <0x52>;
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pagesize = <32>;
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};
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};
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/* console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* eMMC */
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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|
|
|
||
|
|
&wdog1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
||
|
|
fsl,ext-reset-output;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc {
|
||
|
|
pinctrl_fec1: fec1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||
|
|
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||
|
|
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||
|
|
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||
|
|
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||
|
|
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||
|
|
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||
|
|
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||
|
|
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||
|
|
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||
|
|
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||
|
|
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||
|
|
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||
|
|
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||
|
|
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gsc: gscgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||
|
|
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1_gpio: i2c1gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
|
||
|
|
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||
|
|
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
|
||
|
|
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||
|
|
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|