577 lines
14 KiB
Plaintext
577 lines
14 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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#include <dt-bindings/usb/pd.h>
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#include "imx8mn.dtsi"
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/ {
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chosen {
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stdout-path = &uart2;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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status {
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label = "yellow:status";
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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off-on-delay-us = <12000>;
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enable-active-high;
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};
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ir-receiver {
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compatible = "gpio-ir-receiver";
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gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ir>;
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linux,autosuspend-period = <125>;
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};
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audio_codec_bt_sco: audio-codec-bt-sco {
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compatible = "linux,bt-sco";
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#sound-dai-cells = <1>;
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};
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wm8524: audio-codec {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8524";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_wlf>;
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wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
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clock-names = "mclk";
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};
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sound-bt-sco {
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compatible = "simple-audio-card";
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simple-audio-card,name = "bt-sco-audio";
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simple-audio-card,format = "dsp_a";
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simple-audio-card,bitclock-inversion;
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simple-audio-card,frame-master = <&btcpu>;
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simple-audio-card,bitclock-master = <&btcpu>;
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btcpu: simple-audio-card,cpu {
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sound-dai = <&sai2>;
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dai-tdm-slot-num = <2>;
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dai-tdm-slot-width = <16>;
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};
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simple-audio-card,codec {
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sound-dai = <&audio_codec_bt_sco 1>;
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};
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};
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sound-wm8524 {
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compatible = "fsl,imx-audio-wm8524";
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model = "wm8524-audio";
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audio-cpu = <&sai3>;
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audio-codec = <&wm8524>;
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audio-asrc = <&easrc>;
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audio-routing =
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"Line Out Jack", "LINEVOUTL",
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"Line Out Jack", "LINEVOUTR";
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif";
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model = "imx-spdif";
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spdif-controller = <&spdif1>;
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spdif-out;
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spdif-in;
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};
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};
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&easrc {
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fsl,asrc-rate = <48000>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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qca,disable-smarteee;
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vddio-supply = <&vddio>;
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vddio: vddio-regulator {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <166000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
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status = "okay";
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ptn5110: tcpc@50 {
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compatible = "nxp,ptn5110";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec1>;
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reg = <0x50>;
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interrupt-parent = <&gpio2>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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status = "okay";
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port {
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typec1_dr_sw: endpoint {
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remote-endpoint = <&usb1_drd_sw>;
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};
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};
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typec1_con: connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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power-role = "dual";
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data-role = "dual";
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try-power-role = "sink";
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source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
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sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
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PDO_VAR(5000, 20000, 3000)>;
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op-sink-microwatt = <15000000>;
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self-powered;
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};
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};
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-1 = <&pinctrl_i2c3_gpio>;
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scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pca6416: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&sai2 {
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
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assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&spdif1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spdif1>;
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assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
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assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&uart1 { /* BT */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MN_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart2 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MN_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbphynop1 {
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wakeup-source;
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};
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&usbotg1 {
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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usb-role-switch;
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disable-over-current;
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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status = "okay";
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port {
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usb1_drd_sw: endpoint {
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remote-endpoint = <&typec1_dr_sw>;
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};
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};
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
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>;
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};
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pinctrl_flexspi: flexspigrp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
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MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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|
|
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||
|
|
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||
|
|
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio_led: gpioledgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio_wlf: gpiowlfgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ir: irgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||
|
|
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||
|
|
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2_gpio: i2c2grp-gpio {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
|
||
|
|
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3: i2c3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||
|
|
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3_gpio: i2c3grp-gpio {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
|
||
|
|
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pmic: pmicirqgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_sai2: sai2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
|
||
|
|
MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
|
||
|
|
MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
|
||
|
|
MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_sai3: sai3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
||
|
|
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
|
||
|
|
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
|
||
|
|
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_spdif1: spdif1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
|
||
|
|
MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_typec1: typec1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||
|
|
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||
|
|
MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
|
||
|
|
MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||
|
|
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3: uart3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
|
||
|
|
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
|
||
|
|
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
|
||
|
|
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||
|
|
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||
|
|
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||
|
|
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||
|
|
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||
|
|
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||
|
|
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
|
||
|
|
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||
|
|
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
||
|
|
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||
|
|
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
||
|
|
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||
|
|
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|