789 lines
18 KiB
Plaintext
789 lines
18 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mp.dtsi"
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/ {
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model = "NXP i.MX8MPlus EVK board";
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compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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status {
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label = "yellow:status";
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0xc0000000>,
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<0x1 0x00000000 0 0xc0000000>;
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_can1_stby: regulator-can1-stby {
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compatible = "regulator-fixed";
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regulator-name = "can1-stby";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1_reg>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_can2_stby: regulator-can2-stby {
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compatible = "regulator-fixed";
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regulator-name = "can2-stby";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2_reg>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_pcie0: regulator-pcie {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0_reg>;
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regulator-name = "MPCIE_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi0>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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};
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};
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&A53_0 {
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cpu-supply = <®_arm>;
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};
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&A53_1 {
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cpu-supply = <®_arm>;
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};
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&A53_2 {
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cpu-supply = <®_arm>;
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};
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&A53_3 {
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cpu-supply = <®_arm>;
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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snps,force_thresh_dma_mode;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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realtek,clkout-disable;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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snps,tx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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};
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <5>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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snps,map-to-dma-channel = <0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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snps,map-to-dma-channel = <1>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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snps,map-to-dma-channel = <2>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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snps,map-to-dma-channel = <3>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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snps,map-to-dma-channel = <4>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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realtek,clkout-disable;
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};
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can1_stby>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can2_stby>;
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status = "disabled";/* can2 pin conflict with pdm */
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <720000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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reg_arm: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <720000>;
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regulator-max-microvolt = <1025000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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};
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BUCK4 {
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regulator-name = "BUCK4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3600000>;
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regulator-boot-on;
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regulator-always-on;
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};
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BUCK5 {
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regulator-name = "BUCK5";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <1045000>;
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regulator-max-microvolt = <1155000>;
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regulator-boot-on;
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regulator-always-on;
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};
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LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <1710000>;
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regulator-max-microvolt = <1890000>;
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regulator-boot-on;
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regulator-always-on;
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};
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LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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pca6416: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca6416_int>;
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interrupt-parent = <&gpio1>;
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interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
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gpio-line-names = "EXT_PWREN1",
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"EXT_PWREN2",
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"CAN1/I2C5_SEL",
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"PDM/CAN2_SEL",
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"FAN_EN",
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"PWR_MEAS_IO1",
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"PWR_MEAS_IO2",
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"EXP_P0_7",
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"EXP_P1_0",
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"EXP_P1_1",
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"EXP_P1_2",
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"EXP_P1_3",
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"EXP_P1_4",
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"EXP_P1_5",
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"EXP_P1_6",
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"EXP_P1_7";
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};
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};
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/* I2C on expansion connector J22. */
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&i2c5 {
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clock-frequency = <100000>; /* Lower clock speed for external bus. */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c5>;
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status = "disabled"; /* can1 pins conflict with i2c5 */
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/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
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* LOW: CAN1 (default, pull-down)
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* HIGH: I2C5
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* You need to set it to high to enable I2C5 (for example, add gpio-hog
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* in pca6416 node).
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||
|
|
*/
|
||
|
|
};
|
||
|
|
|
||
|
|
&pcie_phy {
|
||
|
|
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||
|
|
clocks = <&pcie0_refclk>;
|
||
|
|
clock-names = "ref";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pcie {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pcie0>;
|
||
|
|
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||
|
|
vpcie-supply = <®_pcie0>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm2 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pwm2>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm4 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pwm4>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&snvs_pwrkey {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart1 { /* BT */
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
||
|
|
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
||
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||
|
|
uart-has-rtscts;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart2 {
|
||
|
|
/* console */
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usb3_phy1 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usb3_1 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usb_dwc3_1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_usb1_vbus>;
|
||
|
|
dr_mode = "host";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart3 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
||
|
|
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
|
||
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||
|
|
uart-has-rtscts;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usdhc2 {
|
||
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
||
|
|
assigned-clock-rates = <400000000>;
|
||
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||
|
|
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
||
|
|
bus-width = <4>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usdhc3 {
|
||
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
||
|
|
assigned-clock-rates = <400000000>;
|
||
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
||
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||
|
|
bus-width = <8>;
|
||
|
|
non-removable;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&wdog1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
||
|
|
fsl,ext-reset-output;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc {
|
||
|
|
pinctrl_eqos: eqosgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
|
||
|
|
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
|
||
|
|
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
|
||
|
|
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
|
||
|
|
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
|
||
|
|
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
|
||
|
|
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
|
||
|
|
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
|
||
|
|
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
|
||
|
|
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
|
||
|
|
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
||
|
|
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
||
|
|
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
||
|
|
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
||
|
|
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_fec: fecgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
|
||
|
|
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
|
||
|
|
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
|
||
|
|
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
|
||
|
|
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
|
||
|
|
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
|
||
|
|
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
|
||
|
|
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
|
||
|
|
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
|
||
|
|
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexcan1: flexcan1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
||
|
|
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexcan2: flexcan2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
|
||
|
|
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexcan1_reg: flexcan1reggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexcan2_reg: flexcan2reggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexspi0: flexspi0grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
|
||
|
|
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
|
||
|
|
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
|
||
|
|
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
|
||
|
|
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
|
||
|
|
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio_led: gpioledgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
|
||
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
|
||
|
|
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3: i2c3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
|
||
|
|
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c5: i2c5grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
|
||
|
|
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pcie0: pcie0grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
|
||
|
|
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pcie0_reg: pcie0reggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pmic: pmicgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pca6416_int: pca6416_int_grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm1: pwm1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm2: pwm2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm4: pwm4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
||
|
|
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
||
|
|
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
|
||
|
|
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
|
||
|
|
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usb1_vbus: usb1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3: uart3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
|
||
|
|
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
|
||
|
|
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
|
||
|
|
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|