52 lines
1.0 KiB
Plaintext
52 lines
1.0 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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&dma_subsys {
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uart4_lpcg: clock-controller@5a4a0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a4a0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "uart4_lpcg_baud_clk",
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"uart4_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_UART_4>;
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};
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};
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&lpuart0 {
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compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
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};
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&lpuart1 {
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compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
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};
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&lpuart2 {
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compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
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};
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&lpuart3 {
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compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
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};
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&i2c0 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&i2c1 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&i2c2 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&i2c3 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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