122 lines
2.6 KiB
Plaintext
122 lines
2.6 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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/dts-v1/;
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#include "imx8ulp.dtsi"
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/ {
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model = "NXP i.MX8ULP EVK";
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compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
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chosen {
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stdout-path = &lpuart5;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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};
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clock_ext_rmii: clock-ext-rmii {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "ext_rmii_clk";
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#clock-cells = <0>;
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};
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clock_ext_ts: clock-ext-ts {
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compatible = "fixed-clock";
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/* External ts clock is 50MHZ from PHY on EVK board. */
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clock-frequency = <50000000>;
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clock-output-names = "ext_ts_clk";
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#clock-cells = <0>;
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};
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};
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&lpuart5 {
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/* console */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpuart5>;
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pinctrl-1 = <&pinctrl_lpuart5>;
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status = "okay";
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};
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&usdhc0 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-1 = <&pinctrl_enet>;
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clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
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<&pcc4 IMX8ULP_CLK_ENET>,
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<&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
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<&clock_ext_rmii>;
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clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
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assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
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assigned-clock-parents = <&clock_ext_ts>;
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phy-mode = "rmii";
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phy-handle = <ðphy>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&iomuxc1 {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX8ULP_PAD_PTE15__ENET0_MDC 0x43
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MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
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MX8ULP_PAD_PTE17__ENET0_RXER 0x43
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MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
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MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
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MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
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MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
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MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
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MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
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MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
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MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
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>;
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};
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX8ULP_PAD_PTF14__LPUART5_TX 0x3
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MX8ULP_PAD_PTF15__LPUART5_RX 0x3
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
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MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
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MX8ULP_PAD_PTD10__SDHC0_D0 0x43
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MX8ULP_PAD_PTD9__SDHC0_D1 0x43
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MX8ULP_PAD_PTD8__SDHC0_D2 0x43
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MX8ULP_PAD_PTD7__SDHC0_D3 0x43
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MX8ULP_PAD_PTD6__SDHC0_D4 0x43
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MX8ULP_PAD_PTD5__SDHC0_D5 0x43
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MX8ULP_PAD_PTD4__SDHC0_D6 0x43
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MX8ULP_PAD_PTD3__SDHC0_D7 0x43
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MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
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>;
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};
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};
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