42 lines
843 B
Plaintext
42 lines
843 B
Plaintext
|
// SPDX-License-Identifier: GPL-2.0
|
||
|
|
/*
|
||
|
|
* Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
|
||
|
|
*
|
||
|
|
* Copyright (C) 2020 Renesas Electronics Corp.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/dts-v1/;
|
||
|
|
#include "r8a774b1.dtsi"
|
||
|
|
#include "hihope-rev4.dtsi"
|
||
|
|
|
||
|
|
/ {
|
||
|
|
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
|
||
|
|
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
|
||
|
|
|
||
|
|
memory@48000000 {
|
||
|
|
device_type = "memory";
|
||
|
|
/* first 128MB is reserved for secure area. */
|
||
|
|
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
memory@480000000 {
|
||
|
|
device_type = "memory";
|
||
|
|
reg = <0x4 0x80000000 0x0 0x80000000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&du {
|
||
|
|
clocks = <&cpg CPG_MOD 724>,
|
||
|
|
<&cpg CPG_MOD 723>,
|
||
|
|
<&cpg CPG_MOD 721>,
|
||
|
|
<&versaclock5 1>,
|
||
|
|
<&x302_clk>,
|
||
|
|
<&versaclock5 2>;
|
||
|
|
clock-names = "du.0", "du.1", "du.3",
|
||
|
|
"dclkin.0", "dclkin.1", "dclkin.3";
|
||
|
|
};
|
||
|
|
|
||
|
|
&sdhi3 {
|
||
|
|
mmc-hs400-1_8v;
|
||
|
|
};
|