88 lines
1.6 KiB
Plaintext
88 lines
1.6 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2LC SMARC EVK parts
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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#include "rzg2lc-smarc-pinfunction.dtsi"
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#include "rz-smarc-common.dtsi"
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/ {
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aliases {
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serial1 = &scif1;
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i2c2 = &i2c2;
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};
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};
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#if (SW_SCIF_CAN || SW_RSPI_CAN)
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&canfd {
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pinctrl-0 = <&can1_pins>;
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/delete-node/ channel@0;
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};
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#else
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&canfd {
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/delete-property/ pinctrl-0;
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/delete-property/ pinctrl-names;
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status = "disabled";
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};
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#endif
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&cpu_dai {
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sound-dai = <&ssi0>;
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};
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&i2c2 {
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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wm8978: codec@1a {
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compatible = "wlf,wm8978";
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#sound-dai-cells = <0>;
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reg = <0x1a>;
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};
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};
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/*
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* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
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* SW1 should be at position 2->3 so that SER0_CTS# line is activated
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* SW2 should be at position 2->3 so that SER0_TX line is activated
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* SW3 should be at position 2->3 so that SER0_RX line is activated
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* SW4 should be at position 2->3 so that SER0_RTS# line is activated
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*/
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#if (!SW_SCIF_CAN && PMOD1_SER0)
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&scif1 {
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pinctrl-0 = <&scif1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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#endif
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&ssi0 {
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pinctrl-0 = <&ssi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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#if (SW_RSPI_CAN)
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&spi1 {
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/delete-property/ pinctrl-0;
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/delete-property/ pinctrl-names;
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status = "disabled";
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};
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#endif
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&vccq_sdhi1 {
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gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
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};
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