59 lines
1.4 KiB
Plaintext
59 lines
1.4 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3588s.dtsi"
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#include "rk3588-pinctrl.dtsi"
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/ {
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "macirq", "eth_wake_irq";
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clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
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<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
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<&cru CLK_GMAC0_PTP_REF>;
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clock-names = "stmmaceth", "clk_mac_ref",
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"pclk_mac", "aclk_mac",
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"ptp_ref";
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power-domains = <&power RK3588_PD_GMAC>;
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resets = <&cru SRST_A_GMAC0>;
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reset-names = "stmmaceth";
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rockchip,grf = <&sys_grf>;
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rockchip,php-grf = <&php_grf>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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snps,mixed-burst;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,tso;
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status = "disabled";
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mdio0: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <0 0 0 0 16 8 4>;
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snps,wr_osr_lmt = <4>;
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snps,rd_osr_lmt = <8>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <2>;
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queue0 {};
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queue1 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <2>;
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queue0 {};
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queue1 {};
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};
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};
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};
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