332 lines
10 KiB
C
332 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_ATOMIC_LL_SC_H
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#define __ASM_ATOMIC_LL_SC_H
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#include <linux/stringify.h>
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#ifndef CONFIG_CC_HAS_K_CONSTRAINT
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#define K
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#endif
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/*
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* AArch64 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*/
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#define ATOMIC_OP(op, asm_op, constraint) \
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static __always_inline void \
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__ll_sc_atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" stxr %w1, %w0, %2\n" \
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" cbnz %w1, 1b\n" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: __stringify(constraint) "r" (i)); \
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}
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#define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
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static __always_inline int \
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__ll_sc_atomic_##op##_return##name(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "_return" #name "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ld" #acq "xr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" st" #rel "xr %w1, %w0, %2\n" \
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" cbnz %w1, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: __stringify(constraint) "r" (i) \
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: cl); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \
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static __always_inline int \
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__ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int val, result; \
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\
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asm volatile("// atomic_fetch_" #op #name "\n" \
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" prfm pstl1strm, %3\n" \
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"1: ld" #acq "xr %w0, %3\n" \
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" " #asm_op " %w1, %w0, %w4\n" \
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" st" #rel "xr %w2, %w1, %3\n" \
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" cbnz %w2, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
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: __stringify(constraint) "r" (i) \
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: cl); \
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\
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return result; \
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}
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#define ATOMIC_OPS(...) \
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ATOMIC_OP(__VA_ARGS__) \
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ATOMIC_OP_RETURN( , dmb ish, , l, "memory", __VA_ARGS__)\
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ATOMIC_OP_RETURN(_relaxed, , , , , __VA_ARGS__)\
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ATOMIC_OP_RETURN(_acquire, , a, , "memory", __VA_ARGS__)\
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ATOMIC_OP_RETURN(_release, , , l, "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_relaxed, , , , , __VA_ARGS__)\
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ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
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ATOMIC_OPS(add, add, I)
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ATOMIC_OPS(sub, sub, J)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(...) \
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ATOMIC_OP(__VA_ARGS__) \
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ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_relaxed, , , , , __VA_ARGS__)\
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ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
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ATOMIC_OPS(and, and, K)
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ATOMIC_OPS(or, orr, K)
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ATOMIC_OPS(xor, eor, K)
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/*
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* GAS converts the mysterious and undocumented BIC (immediate) alias to
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* an AND (immediate) instruction with the immediate inverted. We don't
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* have a constraint for this, so fall back to register.
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*/
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ATOMIC_OPS(andnot, bic, )
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define ATOMIC64_OP(op, asm_op, constraint) \
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static __always_inline void \
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__ll_sc_atomic64_##op(s64 i, atomic64_t *v) \
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{ \
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s64 result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" stxr %w1, %0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: __stringify(constraint) "r" (i)); \
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}
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#define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
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static __always_inline long \
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__ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \
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{ \
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s64 result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "_return" #name "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ld" #acq "xr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" st" #rel "xr %w1, %0, %2\n" \
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" cbnz %w1, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: __stringify(constraint) "r" (i) \
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: cl); \
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\
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return result; \
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}
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#define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\
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static __always_inline long \
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__ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
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{ \
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s64 result, val; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_fetch_" #op #name "\n" \
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" prfm pstl1strm, %3\n" \
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"1: ld" #acq "xr %0, %3\n" \
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" " #asm_op " %1, %0, %4\n" \
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" st" #rel "xr %w2, %1, %3\n" \
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" cbnz %w2, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
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: __stringify(constraint) "r" (i) \
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: cl); \
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\
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return result; \
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}
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#define ATOMIC64_OPS(...) \
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ATOMIC64_OP(__VA_ARGS__) \
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ATOMIC64_OP_RETURN(, dmb ish, , l, "memory", __VA_ARGS__) \
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ATOMIC64_OP_RETURN(_relaxed,, , , , __VA_ARGS__) \
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ATOMIC64_OP_RETURN(_acquire,, a, , "memory", __VA_ARGS__) \
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ATOMIC64_OP_RETURN(_release,, , l, "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_relaxed,, , , , __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_acquire,, a, , "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
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ATOMIC64_OPS(add, add, I)
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ATOMIC64_OPS(sub, sub, J)
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(...) \
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ATOMIC64_OP(__VA_ARGS__) \
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ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_relaxed,, , , , __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_acquire,, a, , "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
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ATOMIC64_OPS(and, and, L)
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ATOMIC64_OPS(or, orr, L)
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ATOMIC64_OPS(xor, eor, L)
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/*
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* GAS converts the mysterious and undocumented BIC (immediate) alias to
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* an AND (immediate) instruction with the immediate inverted. We don't
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* have a constraint for this, so fall back to register.
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*/
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ATOMIC64_OPS(andnot, bic, )
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static __always_inline s64
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__ll_sc_atomic64_dec_if_positive(atomic64_t *v)
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{
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s64 result;
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unsigned long tmp;
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asm volatile("// atomic64_dec_if_positive\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %0, %2\n"
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" subs %0, %0, #1\n"
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" b.lt 2f\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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" dmb ish\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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:
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: "cc", "memory");
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return result;
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}
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#define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \
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static __always_inline u##sz \
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__ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
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unsigned long old, \
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u##sz new) \
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{ \
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unsigned long tmp; \
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u##sz oldval; \
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\
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/* \
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* Sub-word sizes require explicit casting so that the compare \
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* part of the cmpxchg doesn't end up interpreting non-zero \
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* upper bits of the register containing "old". \
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*/ \
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if (sz < 32) \
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old = (u##sz)old; \
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\
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asm volatile( \
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" prfm pstl1strm, %[v]\n" \
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"1: ld" #acq "xr" #sfx "\t%" #w "[oldval], %[v]\n" \
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" eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \
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" cbnz %" #w "[tmp], 2f\n" \
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" st" #rel "xr" #sfx "\t%w[tmp], %" #w "[new], %[v]\n" \
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" cbnz %w[tmp], 1b\n" \
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" " #mb "\n" \
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"2:" \
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: [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
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[v] "+Q" (*(u##sz *)ptr) \
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: [old] __stringify(constraint) "r" (old), [new] "r" (new) \
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: cl); \
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\
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return oldval; \
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}
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/*
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* Earlier versions of GCC (no later than 8.1.0) appear to incorrectly
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* handle the 'K' constraint for the value 4294967295 - thus we use no
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* constraint for 32 bit operations.
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*/
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__CMPXCHG_CASE(w, b, , 8, , , , , K)
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__CMPXCHG_CASE(w, h, , 16, , , , , K)
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__CMPXCHG_CASE(w, , , 32, , , , , K)
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__CMPXCHG_CASE( , , , 64, , , , , L)
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__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", K)
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__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", K)
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__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", K)
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__CMPXCHG_CASE( , , acq_, 64, , a, , "memory", L)
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__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", K)
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__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", K)
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__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", K)
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__CMPXCHG_CASE( , , rel_, 64, , , l, "memory", L)
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__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
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__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
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__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", K)
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__CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L)
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#undef __CMPXCHG_CASE
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#define __CMPXCHG_DBL(name, mb, rel, cl) \
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static __always_inline long \
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__ll_sc__cmpxchg_double##name(unsigned long old1, \
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unsigned long old2, \
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unsigned long new1, \
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unsigned long new2, \
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volatile void *ptr) \
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{ \
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unsigned long tmp, ret; \
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\
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asm volatile("// __cmpxchg_double" #name "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ldxp %0, %1, %2\n" \
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" eor %0, %0, %3\n" \
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" eor %1, %1, %4\n" \
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" orr %1, %0, %1\n" \
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" cbnz %1, 2f\n" \
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" st" #rel "xp %w0, %5, %6, %2\n" \
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" cbnz %w0, 1b\n" \
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" " #mb "\n" \
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"2:" \
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|
: "=&r" (tmp), "=&r" (ret), "+Q" (*(__uint128_t *)ptr) \
|
||
|
|
: "r" (old1), "r" (old2), "r" (new1), "r" (new2) \
|
||
|
|
: cl); \
|
||
|
|
\
|
||
|
|
return ret; \
|
||
|
|
}
|
||
|
|
|
||
|
|
__CMPXCHG_DBL( , , , )
|
||
|
|
__CMPXCHG_DBL(_mb, dmb ish, l, "memory")
|
||
|
|
|
||
|
|
#undef __CMPXCHG_DBL
|
||
|
|
#undef K
|
||
|
|
|
||
|
|
#endif /* __ASM_ATOMIC_LL_SC_H */
|