312 lines
9.3 KiB
C
312 lines
9.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM64_KVM_MMU_H__
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#define __ARM64_KVM_MMU_H__
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#include <asm/page.h>
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#include <asm/memory.h>
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#include <asm/mmu.h>
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#include <asm/cpufeature.h>
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/*
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* As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
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* "negative" addresses. This makes it impossible to directly share
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* mappings with the kernel.
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*
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* Instead, give the HYP mode its own VA region at a fixed offset from
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* the kernel by just masking the top bits (which are all ones for a
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* kernel address). We need to find out how many bits to mask.
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*
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* We want to build a set of page tables that cover both parts of the
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* idmap (the trampoline page used to initialize EL2), and our normal
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* runtime VA space, at the same time.
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*
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* Given that the kernel uses VA_BITS for its entire address space,
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* and that half of that space (VA_BITS - 1) is used for the linear
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* mapping, we can also limit the EL2 space to (VA_BITS - 1).
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*
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* The main question is "Within the VA_BITS space, does EL2 use the
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* top or the bottom half of that space to shadow the kernel's linear
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* mapping?". As we need to idmap the trampoline page, this is
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* determined by the range in which this page lives.
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*
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* If the page is in the bottom half, we have to use the top half. If
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* the page is in the top half, we have to use the bottom half:
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*
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* T = __pa_symbol(__hyp_idmap_text_start)
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* if (T & BIT(VA_BITS - 1))
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* HYP_VA_MIN = 0 //idmap in upper half
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* else
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* HYP_VA_MIN = 1 << (VA_BITS - 1)
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* HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
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*
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* When using VHE, there are no separate hyp mappings and all KVM
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* functionality is already mapped as part of the main kernel
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* mappings, and none of this applies in that case.
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*/
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#ifdef __ASSEMBLY__
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#include <asm/alternative.h>
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/*
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* Convert a kernel VA into a HYP VA.
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* reg: VA to be converted.
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*
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* The actual code generation takes place in kvm_update_va_mask, and
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* the instructions below are only there to reserve the space and
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* perform the register allocation (kvm_update_va_mask uses the
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* specific registers encoded in the instructions).
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*/
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.macro kern_hyp_va reg
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alternative_cb ARM64_ALWAYS_SYSTEM, kvm_update_va_mask
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and \reg, \reg, #1 /* mask with va_mask */
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ror \reg, \reg, #1 /* rotate to the first tag bit */
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add \reg, \reg, #0 /* insert the low 12 bits of the tag */
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add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */
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ror \reg, \reg, #63 /* rotate back */
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alternative_cb_end
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.endm
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/*
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* Convert a hypervisor VA to a PA
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* reg: hypervisor address to be converted in place
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* tmp: temporary register
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*/
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.macro hyp_pa reg, tmp
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ldr_l \tmp, hyp_physvirt_offset
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add \reg, \reg, \tmp
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.endm
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/*
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* Convert a hypervisor VA to a kernel image address
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* reg: hypervisor address to be converted in place
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* tmp: temporary register
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*
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* The actual code generation takes place in kvm_get_kimage_voffset, and
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* the instructions below are only there to reserve the space and
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* perform the register allocation (kvm_get_kimage_voffset uses the
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* specific registers encoded in the instructions).
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*/
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.macro hyp_kimg_va reg, tmp
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/* Convert hyp VA -> PA. */
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hyp_pa \reg, \tmp
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/* Load kimage_voffset. */
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alternative_cb ARM64_ALWAYS_SYSTEM, kvm_get_kimage_voffset
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movz \tmp, #0
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movk \tmp, #0, lsl #16
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movk \tmp, #0, lsl #32
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movk \tmp, #0, lsl #48
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alternative_cb_end
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/* Convert PA -> kimg VA. */
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add \reg, \reg, \tmp
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.endm
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#else
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#include <linux/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_host.h>
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void kvm_update_va_mask(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst);
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void kvm_compute_layout(void);
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void kvm_apply_hyp_relocations(void);
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#define __hyp_pa(x) (((phys_addr_t)(x)) + hyp_physvirt_offset)
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static __always_inline unsigned long __kern_hyp_va(unsigned long v)
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{
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asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
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"ror %0, %0, #1\n"
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"add %0, %0, #0\n"
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"add %0, %0, #0, lsl 12\n"
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"ror %0, %0, #63\n",
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ARM64_ALWAYS_SYSTEM,
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kvm_update_va_mask)
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: "+r" (v));
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return v;
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}
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#define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v))))
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/*
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* We currently support using a VM-specified IPA size. For backward
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* compatibility, the default IPA size is fixed to 40bits.
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*/
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#define KVM_PHYS_SHIFT (40)
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#define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr)
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#define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm))
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#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL))
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#include <asm/kvm_pgtable.h>
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#include <asm/stage2_pgtable.h>
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int kvm_share_hyp(void *from, void *to);
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void kvm_unshare_hyp(void *from, void *to);
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int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot);
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int __create_hyp_mappings(unsigned long start, unsigned long size,
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unsigned long phys, enum kvm_pgtable_prot prot);
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int hyp_alloc_private_va_range(size_t size, unsigned long *haddr);
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int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
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void __iomem **kaddr,
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void __iomem **haddr);
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int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
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void **haddr);
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void __init free_hyp_pgds(void);
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void stage2_unmap_vm(struct kvm *kvm);
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int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long type);
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void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size, bool writable);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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int __init kvm_mmu_init(u32 *hyp_va_bits);
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static inline void *__kvm_vector_slot2addr(void *base,
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enum arm64_hyp_spectre_vector slot)
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{
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int idx = slot - (slot != HYP_VECTOR_DIRECT);
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return base + (idx * SZ_2K);
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}
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) \
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dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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u64 cache_bits = SCTLR_ELx_M | SCTLR_ELx_C;
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int reg;
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if (vcpu_is_el2(vcpu))
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reg = SCTLR_EL2;
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else
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reg = SCTLR_EL1;
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return (vcpu_read_sys_reg(vcpu, reg) & cache_bits) == cache_bits;
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}
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static inline void __clean_dcache_guest_page(void *va, size_t size)
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{
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/*
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* With FWB, we ensure that the guest always accesses memory using
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* cacheable attributes, and we don't have to clean to PoC when
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* faulting in pages. Furthermore, FWB implies IDC, so cleaning to
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* PoU is not required either in this case.
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*/
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if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
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return;
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kvm_flush_dcache_to_poc(va, size);
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}
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static inline void __invalidate_icache_guest_page(void *va, size_t size)
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{
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if (icache_is_aliasing()) {
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/* any kind of VIPT cache */
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icache_inval_all_pou();
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} else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) {
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/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */
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icache_inval_pou((unsigned long)va, (unsigned long)va + size);
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}
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}
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void kvm_set_way_flush(struct kvm_vcpu *vcpu);
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void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
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static inline unsigned int kvm_get_vmid_bits(void)
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{
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int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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return get_vmid_bits(reg);
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}
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/*
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* We are not in the kvm->srcu critical section most of the time, so we take
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* the SRCU read lock here. Since we copy the data from the user page, we
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* can immediately drop the lock again.
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*/
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static inline int kvm_read_guest_lock(struct kvm *kvm,
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gpa_t gpa, void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_read_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
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const void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_write_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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#define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr)
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/*
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* When this is (directly or indirectly) used on the TLB invalidation
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* path, we rely on a previously issued DSB so that page table updates
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* and VMID reads are correctly ordered.
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*/
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static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
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{
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struct kvm_vmid *vmid = &mmu->vmid;
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u64 vmid_field, baddr;
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u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0;
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baddr = mmu->pgd_phys;
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vmid_field = atomic64_read(&vmid->id) << VTTBR_VMID_SHIFT;
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vmid_field &= VTTBR_VMID_MASK(kvm_arm_vmid_bits);
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return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
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}
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/*
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* Must be called from hyp code running at EL2 with an updated VTTBR
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* and interrupts disabled.
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*/
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static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu,
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struct kvm_arch *arch)
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{
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write_sysreg(arch->vtcr, vtcr_el2);
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write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
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/*
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* ARM errata 1165522 and 1530923 require the actual execution of the
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* above before we can switch to the EL1/EL0 translation regime used by
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* the guest.
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
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}
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static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu)
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{
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return container_of(mmu->arch, struct kvm, arch);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ARM64_KVM_MMU_H__ */
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