143 lines
5.9 KiB
C
143 lines
5.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Author: Huacai Chen <chenhuacai@loongson.cn>
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_LOONGSON_H
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#define __ASM_LOONGSON_H
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#define LOONGSON_REG(x) \
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(*(volatile u32 *)((char *)TO_UNCACHE(LOONGSON_REG_BASE) + (x)))
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#define LOONGSON_LIO_BASE 0x18000000
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#define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
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#define LOONGSON_LIO_TOP (LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1)
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#define LOONGSON_BOOT_BASE 0x1c000000
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#define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
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#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
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#define LOONGSON_REG_BASE 0x1fe00000
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#define LOONGSON_REG_SIZE 0x00100000 /* 1M */
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#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
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/* GPIO Regs - r/w */
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#define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
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#define LOONGSON_GPIOIE LOONGSON_REG(0x120)
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#define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
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#define MAX_PACKAGES 16
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#define xconf_readl(addr) readl(addr)
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#define xconf_readq(addr) readq(addr)
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static inline void xconf_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile (
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" st.w %[v], %[hw], 0 \n"
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" ld.b $zero, %[hw], 0 \n"
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:
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: [hw] "r" (addr), [v] "r" (val)
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);
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}
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static inline void xconf_writeq(u64 val64, volatile void __iomem *addr)
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{
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asm volatile (
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" st.d %[v], %[hw], 0 \n"
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" ld.b $zero, %[hw], 0 \n"
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:
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: [hw] "r" (addr), [v] "r" (val64)
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);
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}
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/* ============== LS7A registers =============== */
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#define LS7A_PCH_REG_BASE 0x10000000UL
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/* LPC regs */
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#define LS7A_LPC_REG_BASE (LS7A_PCH_REG_BASE + 0x00002000)
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/* CHIPCFG regs */
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#define LS7A_CHIPCFG_REG_BASE (LS7A_PCH_REG_BASE + 0x00010000)
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/* MISC reg base */
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#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000)
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/* ACPI regs */
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#define LS7A_ACPI_REG_BASE (LS7A_MISC_REG_BASE + 0x00050000)
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/* RTC regs */
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#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100)
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#define LS7A_DMA_CFG (volatile void *)TO_UNCACHE(LS7A_CHIPCFG_REG_BASE + 0x041c)
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#define LS7A_DMA_NODE_SHF 8
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#define LS7A_DMA_NODE_MASK 0x1F00
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#define LS7A_INT_MASK_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x020)
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#define LS7A_INT_EDGE_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x060)
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#define LS7A_INT_CLEAR_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x080)
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#define LS7A_INT_HTMSI_EN_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x040)
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#define LS7A_INT_ROUTE_ENTRY_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x100)
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#define LS7A_INT_HTMSI_VEC_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200)
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#define LS7A_INT_STATUS_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3a0)
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#define LS7A_INT_POL_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3e0)
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#define LS7A_LPC_INT_CTL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2000)
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#define LS7A_LPC_INT_ENA (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2004)
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#define LS7A_LPC_INT_STS (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2008)
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#define LS7A_LPC_INT_CLR (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200c)
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#define LS7A_LPC_INT_POL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2010)
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#define LS7A_PMCON_SOC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x000)
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#define LS7A_PMCON_RESUME_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x004)
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#define LS7A_PMCON_RTC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x008)
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#define LS7A_PM1_EVT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x00c)
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#define LS7A_PM1_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x010)
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#define LS7A_PM1_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x014)
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#define LS7A_PM1_TMR_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x018)
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#define LS7A_P_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x01c)
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#define LS7A_GPE0_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x028)
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#define LS7A_GPE0_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x02c)
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#define LS7A_RST_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x030)
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#define LS7A_WD_SET_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x034)
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#define LS7A_WD_TIMER_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x038)
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#define LS7A_THSENS_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x04c)
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#define LS7A_GEN_RTC_1_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x050)
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#define LS7A_GEN_RTC_2_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x054)
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#define LS7A_DPM_CFG_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x400)
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#define LS7A_DPM_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x404)
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#define LS7A_DPM_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x408)
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typedef enum {
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ACPI_PCI_HOTPLUG_STATUS = 1 << 1,
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ACPI_CPU_HOTPLUG_STATUS = 1 << 2,
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ACPI_MEM_HOTPLUG_STATUS = 1 << 3,
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ACPI_POWERBUTTON_STATUS = 1 << 8,
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ACPI_RTC_WAKE_STATUS = 1 << 10,
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ACPI_PCI_WAKE_STATUS = 1 << 14,
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ACPI_ANY_WAKE_STATUS = 1 << 15,
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} AcpiEventStatusBits;
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#define HT1LO_OFFSET 0xe0000000000UL
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/* PCI Configuration Space Base */
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#define MCFG_EXT_PCICFG_BASE 0xefe00000000UL
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/* REG ACCESS*/
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#define ls7a_readb(addr) (*(volatile unsigned char *)TO_UNCACHE(addr))
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#define ls7a_readw(addr) (*(volatile unsigned short *)TO_UNCACHE(addr))
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#define ls7a_readl(addr) (*(volatile unsigned int *)TO_UNCACHE(addr))
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#define ls7a_readq(addr) (*(volatile unsigned long *)TO_UNCACHE(addr))
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#define ls7a_writeb(val, addr) *(volatile unsigned char *)TO_UNCACHE(addr) = (val)
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#define ls7a_writew(val, addr) *(volatile unsigned short *)TO_UNCACHE(addr) = (val)
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#define ls7a_writel(val, addr) *(volatile unsigned int *)TO_UNCACHE(addr) = (val)
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#define ls7a_writeq(val, addr) *(volatile unsigned long *)TO_UNCACHE(addr) = (val)
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void enable_gpe_wakeup(void);
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void enable_pci_wakeup(void);
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#endif /* __ASM_LOONGSON_H */
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