100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#ifndef _MT7620_REGS_H_
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#define _MT7620_REGS_H_
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#define MT7620_SYSC_BASE 0x10000000
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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#define SYSC_REG_EFUSE_CFG 0x08
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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#define SYSC_REG_CLKCFG0 0x2c
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#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
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#define SYSC_REG_CPLL_CONFIG0 0x54
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#define SYSC_REG_CPLL_CONFIG1 0x58
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#define MT7620_CHIP_NAME0 0x3637544d
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#define MT7620_CHIP_NAME1 0x20203032
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#define MT7628_CHIP_NAME1 0x20203832
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#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
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#define CHIP_REV_PKG_MASK 0x1
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#define CHIP_REV_PKG_SHIFT 16
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#define CHIP_REV_VER_MASK 0xf
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#define CHIP_REV_VER_SHIFT 8
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#define CHIP_REV_ECO_MASK 0xf
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#define CLKCFG0_PERI_CLK_SEL BIT(4)
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#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
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#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
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#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
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#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
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#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
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#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
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#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
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#define CPLL_CFG0_SW_CFG BIT(31)
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#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
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#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
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#define CPLL_CFG0_LC_CURFCK BIT(15)
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#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
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#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
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#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
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#define CPLL_CFG1_CPU_AUX1 BIT(25)
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#define CPLL_CFG1_CPU_AUX0 BIT(24)
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#define SYSCFG0_DRAM_TYPE_MASK 0x3
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#define SYSCFG0_DRAM_TYPE_SHIFT 4
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#define SYSCFG0_DRAM_TYPE_SDRAM 0
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#define SYSCFG0_DRAM_TYPE_DDR1 1
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#define SYSCFG0_DRAM_TYPE_DDR2 2
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#define SYSCFG0_DRAM_TYPE_UNKNOWN 3
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#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
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#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
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#define MT7620_DRAM_BASE 0x0
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#define MT7620_SDRAM_SIZE_MIN 2
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#define MT7620_SDRAM_SIZE_MAX 64
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#define MT7620_DDR1_SIZE_MIN 32
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#define MT7620_DDR1_SIZE_MAX 128
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#define MT7620_DDR2_SIZE_MIN 32
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#define MT7620_DDR2_SIZE_MAX 256
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extern enum ralink_soc_type ralink_soc;
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static inline int is_mt76x8(void)
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{
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return ralink_soc == MT762X_SOC_MT7628AN ||
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ralink_soc == MT762X_SOC_MT7688;
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}
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static inline int mt7620_get_eco(void)
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{
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return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
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}
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#endif
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