196 lines
4.2 KiB
ArmAsm
196 lines
4.2 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Signal trampolines for 32 bit processes.
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*
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* Copyright (C) 2006 Randolph Chung <tausq@debian.org>
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* Copyright (C) 2018-2022 Helge Deller <deller@gmx.de>
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* Copyright (C) 2022 John David Anglin <dave.anglin@bell.net>
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*/
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#include <asm/unistd.h>
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#include <linux/linkage.h>
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#include <generated/asm-offsets.h>
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.text
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/* Gdb expects the trampoline is on the stack and the pc is offset from
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a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline
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is not on the stack, we need a new variant with different offsets and
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data to tell gdb where to find the signal context on the stack.
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Here we put the offset to the context data at the start of the trampoline
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region and offset the first trampoline by 2 instructions. Please do
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not change the trampoline as the code in gdb depends on the following
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instruction sequence exactly.
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*/
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.align 64
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.word SIGFRAME_CONTEXT_REGS32
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/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from
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the return address to get an address in the middle of the presumed
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call instruction. Since we don't have a call here, we artifically
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extend the range covered by the unwind info by adding a nop before
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the real start.
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*/
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nop
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.globl __kernel_sigtramp_rt
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.type __kernel_sigtramp_rt, @function
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__kernel_sigtramp_rt:
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.proc
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.callinfo FRAME=ASM_SIGFRAME_SIZE32,CALLS,SAVE_RP
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.entry
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.Lsigrt_start = . - 4
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0: ldi 0, %r25 /* (in_syscall=0) */
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ldi __NR_rt_sigreturn, %r20
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ble 0x100(%sr2, %r0)
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nop
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1: ldi 1, %r25 /* (in_syscall=1) */
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ldi __NR_rt_sigreturn, %r20
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ble 0x100(%sr2, %r0)
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nop
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.Lsigrt_end:
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.exit
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.procend
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.size __kernel_sigtramp_rt,.-__kernel_sigtramp_rt
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.section .eh_frame,"a",@progbits
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/* This is where the mcontext_t struct can be found on the stack. */
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#define PTREGS SIGFRAME_CONTEXT_REGS32 /* 32-bit process offset is -672 */
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/* Register REGNO can be found at offset OFS of the mcontext_t structure. */
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.macro rsave regno,ofs
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.byte 0x05 /* DW_CFA_offset_extended */
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.uleb128 \regno; /* regno */
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.uleb128 \ofs /* factored offset */
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.endm
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.Lcie:
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.long .Lcie_end - .Lcie_start
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.Lcie_start:
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.long 0 /* CIE ID */
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.byte 1 /* Version number */
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.stringz "zRS" /* NUL-terminated augmentation string */
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.uleb128 4 /* Code alignment factor */
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.sleb128 4 /* Data alignment factor */
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.byte 89 /* Return address register column, iaoq[0] */
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.uleb128 1 /* Augmentation value length */
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.byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
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.byte 0x0f /* DW_CFA_def_cfa_expresion */
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.uleb128 9f - 1f /* length */
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1:
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.byte 0x8e /* DW_OP_breg30 */
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.sleb128 PTREGS
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9:
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.balign 4
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.Lcie_end:
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.long .Lfde0_end - .Lfde0_start
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.Lfde0_start:
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.long .Lfde0_start - .Lcie /* CIE pointer. */
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.long .Lsigrt_start - . /* PC start, length */
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.long .Lsigrt_end - .Lsigrt_start
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.uleb128 0 /* Augmentation */
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/* General registers */
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rsave 1, 2
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rsave 2, 3
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rsave 3, 4
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rsave 4, 5
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rsave 5, 6
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rsave 6, 7
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rsave 7, 8
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rsave 8, 9
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rsave 9, 10
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rsave 10, 11
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rsave 11, 12
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rsave 12, 13
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rsave 13, 14
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rsave 14, 15
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rsave 15, 16
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rsave 16, 17
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rsave 17, 18
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rsave 18, 19
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rsave 19, 20
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rsave 20, 21
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rsave 21, 22
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rsave 22, 23
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rsave 23, 24
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rsave 24, 25
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rsave 25, 26
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rsave 26, 27
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rsave 27, 28
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rsave 28, 29
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rsave 29, 30
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rsave 30, 31
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rsave 31, 32
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/* Floating-point registers */
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rsave 32, 42
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rsave 33, 43
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rsave 34, 44
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rsave 35, 45
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rsave 36, 46
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rsave 37, 47
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rsave 38, 48
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rsave 39, 49
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rsave 40, 50
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rsave 41, 51
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rsave 42, 52
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rsave 43, 53
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rsave 44, 54
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rsave 45, 55
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rsave 46, 56
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rsave 47, 57
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rsave 48, 58
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rsave 49, 59
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rsave 50, 60
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rsave 51, 61
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rsave 52, 62
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rsave 53, 63
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rsave 54, 64
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rsave 55, 65
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rsave 56, 66
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rsave 57, 67
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rsave 58, 68
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rsave 59, 69
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rsave 60, 70
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rsave 61, 71
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rsave 62, 72
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rsave 63, 73
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rsave 64, 74
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rsave 65, 75
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rsave 66, 76
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rsave 67, 77
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rsave 68, 78
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rsave 69, 79
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rsave 70, 80
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rsave 71, 81
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rsave 72, 82
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rsave 73, 83
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rsave 74, 84
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rsave 75, 85
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rsave 76, 86
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rsave 77, 87
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rsave 78, 88
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rsave 79, 89
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rsave 80, 90
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rsave 81, 91
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rsave 82, 92
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rsave 83, 93
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rsave 84, 94
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rsave 85, 95
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rsave 86, 96
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rsave 87, 97
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/* SAR register */
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rsave 88, 102
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/* iaoq[0] return address register */
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rsave 89, 100
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.balign 4
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.Lfde0_end:
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