77 lines
1.7 KiB
Plaintext
77 lines
1.7 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
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#include "sunxi-d1s-t113.dtsi"
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/ {
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cpus {
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timebase-frequency = <24000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "thead,c906", "riscv";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_RISCV>;
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d-cache-block-size = <64>;
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d-cache-sets = <256>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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operating-points-v2 = <&opp_table_cpu>;
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riscv,isa = "rv64imafdc";
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#cooling-cells = <2>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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opp_table_cpu: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000 900000 1100000>;
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};
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opp-1080000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <900000 900000 1100000>;
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};
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};
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soc {
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interrupt-parent = <&plic>;
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riscv_wdt: watchdog@6011000 {
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compatible = "allwinner,sun20i-d1-wdt";
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reg = <0x6011000 0x20>;
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interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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};
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plic: interrupt-controller@10000000 {
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compatible = "allwinner,sun20i-d1-plic",
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"thead,c900-plic";
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reg = <0x10000000 0x4000000>;
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interrupts-extended = <&cpu0_intc 11>,
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<&cpu0_intc 9>;
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interrupt-controller;
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riscv,ndev = <175>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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};
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};
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};
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