199 lines
4.1 KiB
C
199 lines
4.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0
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*
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* include/asm-sh/spinlock-llsc.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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* Copyright (C) 2006, 2007 Akio Idehara
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*/
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#ifndef __ASM_SH_SPINLOCK_LLSC_H
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#define __ASM_SH_SPINLOCK_LLSC_H
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#include <asm/barrier.h>
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#include <asm/processor.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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#define arch_spin_is_locked(x) ((x)->lock <= 0)
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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unsigned long oldval;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! arch_spin_lock \n\t"
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"mov %0, %1 \n\t"
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"mov #0, %0 \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"cmp/pl %1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&lock->lock)
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: "t", "memory"
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);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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/* This could be optimised with ARCH_HAS_MMIOWB */
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mmiowb();
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__asm__ __volatile__ (
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"mov #1, %0 ! arch_spin_unlock \n\t"
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"mov.l %0, @%1 \n\t"
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: "=&z" (tmp)
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: "r" (&lock->lock)
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: "t", "memory"
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);
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned long tmp, oldval;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! arch_spin_trylock \n\t"
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"mov %0, %1 \n\t"
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"mov #0, %0 \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"synco \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&lock->lock)
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: "t", "memory"
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);
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return oldval;
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts but no interrupt
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* writers. For those circumstances we can "mix" irq-safe locks - any writer
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* needs to get a irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%1, %0 ! arch_read_lock \n\t"
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"cmp/pl %0 \n\t"
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"bf 1b \n\t"
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"add #-1, %0 \n\t"
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"movco.l %0, @%1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp)
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: "r" (&rw->lock)
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: "t", "memory"
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);
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%1, %0 ! arch_read_unlock \n\t"
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"add #1, %0 \n\t"
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"movco.l %0, @%1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp)
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: "r" (&rw->lock)
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: "t", "memory"
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);
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%1, %0 ! arch_write_lock \n\t"
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"cmp/hs %2, %0 \n\t"
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"bf 1b \n\t"
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"sub %2, %0 \n\t"
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"movco.l %0, @%1 \n\t"
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"bf 1b \n\t"
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: "=&z" (tmp)
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: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
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: "t", "memory"
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);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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__asm__ __volatile__ (
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"mov.l %1, @%0 ! arch_write_unlock \n\t"
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:
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: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
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: "t", "memory"
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);
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned long tmp, oldval;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! arch_read_trylock \n\t"
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"mov %0, %1 \n\t"
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"cmp/pl %0 \n\t"
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"bf 2f \n\t"
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"add #-1, %0 \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"2: \n\t"
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"synco \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&rw->lock)
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: "t", "memory"
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);
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return (oldval > 0);
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned long tmp, oldval;
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__asm__ __volatile__ (
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"1: \n\t"
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"movli.l @%2, %0 ! arch_write_trylock \n\t"
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"mov %0, %1 \n\t"
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"cmp/hs %3, %0 \n\t"
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"bf 2f \n\t"
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"sub %3, %0 \n\t"
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"2: \n\t"
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"movco.l %0, @%2 \n\t"
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"bf 1b \n\t"
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"synco \n\t"
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: "=&z" (tmp), "=&r" (oldval)
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: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
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: "t", "memory"
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);
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return (oldval > (RW_LOCK_BIAS - 1));
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}
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#endif /* __ASM_SH_SPINLOCK_LLSC_H */
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