576 lines
15 KiB
C
576 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_NOSPEC_BRANCH_H_
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#define _ASM_X86_NOSPEC_BRANCH_H_
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#include <linux/static_key.h>
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#include <linux/objtool.h>
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/cpufeatures.h>
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#include <asm/msr-index.h>
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#include <asm/unwind_hints.h>
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#include <asm/percpu.h>
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#include <asm/current.h>
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/*
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* Call depth tracking for Intel SKL CPUs to address the RSB underflow
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* issue in software.
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*
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* The tracking does not use a counter. It uses uses arithmetic shift
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* right on call entry and logical shift left on return.
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*
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* The depth tracking variable is initialized to 0x8000.... when the call
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* depth is zero. The arithmetic shift right sign extends the MSB and
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* saturates after the 12th call. The shift count is 5 for both directions
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* so the tracking covers 12 nested calls.
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*
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* Call
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* 0: 0x8000000000000000 0x0000000000000000
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* 1: 0xfc00000000000000 0xf000000000000000
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* ...
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* 11: 0xfffffffffffffff8 0xfffffffffffffc00
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* 12: 0xffffffffffffffff 0xffffffffffffffe0
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*
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* After a return buffer fill the depth is credited 12 calls before the
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* next stuffing has to take place.
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*
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* There is a inaccuracy for situations like this:
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*
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* 10 calls
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* 5 returns
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* 3 calls
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* 4 returns
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* 3 calls
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* ....
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*
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* The shift count might cause this to be off by one in either direction,
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* but there is still a cushion vs. the RSB depth. The algorithm does not
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* claim to be perfect and it can be speculated around by the CPU, but it
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* is considered that it obfuscates the problem enough to make exploitation
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* extremly difficult.
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*/
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#define RET_DEPTH_SHIFT 5
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#define RSB_RET_STUFF_LOOPS 16
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#define RET_DEPTH_INIT 0x8000000000000000ULL
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#define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL
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#define RET_DEPTH_CREDIT 0xffffffffffffffffULL
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#ifdef CONFIG_CALL_THUNKS_DEBUG
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# define CALL_THUNKS_DEBUG_INC_CALLS \
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incq %gs:__x86_call_count;
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# define CALL_THUNKS_DEBUG_INC_RETS \
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incq %gs:__x86_ret_count;
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# define CALL_THUNKS_DEBUG_INC_STUFFS \
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incq %gs:__x86_stuffs_count;
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# define CALL_THUNKS_DEBUG_INC_CTXSW \
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incq %gs:__x86_ctxsw_count;
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#else
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# define CALL_THUNKS_DEBUG_INC_CALLS
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# define CALL_THUNKS_DEBUG_INC_RETS
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# define CALL_THUNKS_DEBUG_INC_STUFFS
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# define CALL_THUNKS_DEBUG_INC_CTXSW
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#endif
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#if defined(CONFIG_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS)
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#include <asm/asm-offsets.h>
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#define CREDIT_CALL_DEPTH \
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movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
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#define ASM_CREDIT_CALL_DEPTH \
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movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
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#define RESET_CALL_DEPTH \
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mov $0x80, %rax; \
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shl $56, %rax; \
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movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);
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#define RESET_CALL_DEPTH_FROM_CALL \
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mov $0xfc, %rax; \
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shl $56, %rax; \
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movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
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CALL_THUNKS_DEBUG_INC_CALLS
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#define INCREMENT_CALL_DEPTH \
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sarq $5, %gs:pcpu_hot + X86_call_depth; \
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CALL_THUNKS_DEBUG_INC_CALLS
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#define ASM_INCREMENT_CALL_DEPTH \
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sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
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CALL_THUNKS_DEBUG_INC_CALLS
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#else
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#define CREDIT_CALL_DEPTH
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#define ASM_CREDIT_CALL_DEPTH
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#define RESET_CALL_DEPTH
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#define INCREMENT_CALL_DEPTH
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#define ASM_INCREMENT_CALL_DEPTH
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#define RESET_CALL_DEPTH_FROM_CALL
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#endif
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/*
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* Fill the CPU return stack buffer.
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*
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* Each entry in the RSB, if used for a speculative 'ret', contains an
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* infinite 'pause; lfence; jmp' loop to capture speculative execution.
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*
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* This is required in various cases for retpoline and IBRS-based
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* mitigations for the Spectre variant 2 vulnerability. Sometimes to
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* eliminate potentially bogus entries from the RSB, and sometimes
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* purely to ensure that it doesn't get empty, which on some CPUs would
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* allow predictions from other (unwanted!) sources to be used.
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*
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* We define a CPP macro such that it can be used from both .S files and
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* inline assembly. It's possible to do a .macro and then include that
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* from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
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*/
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#define RETPOLINE_THUNK_SIZE 32
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#define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
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/*
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* Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
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*/
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#define __FILL_RETURN_SLOT \
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ANNOTATE_INTRA_FUNCTION_CALL; \
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call 772f; \
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int3; \
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772:
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/*
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* Stuff the entire RSB.
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*
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* Google experimented with loop-unrolling and this turned out to be
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* the optimal version - two calls, each with their own speculation
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* trap should their return address end up getting used, in a loop.
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*/
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#ifdef CONFIG_X86_64
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#define __FILL_RETURN_BUFFER(reg, nr) \
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mov $(nr/2), reg; \
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771: \
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__FILL_RETURN_SLOT \
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__FILL_RETURN_SLOT \
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add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
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dec reg; \
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jnz 771b; \
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/* barrier for jnz misprediction */ \
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lfence; \
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ASM_CREDIT_CALL_DEPTH \
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CALL_THUNKS_DEBUG_INC_CTXSW
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#else
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/*
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* i386 doesn't unconditionally have LFENCE, as such it can't
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* do a loop.
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*/
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#define __FILL_RETURN_BUFFER(reg, nr) \
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.rept nr; \
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__FILL_RETURN_SLOT; \
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.endr; \
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add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
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#endif
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/*
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* Stuff a single RSB slot.
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*
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* To mitigate Post-Barrier RSB speculation, one CALL instruction must be
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* forced to retire before letting a RET instruction execute.
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*
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* On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
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* before this point.
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*/
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#define __FILL_ONE_RETURN \
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__FILL_RETURN_SLOT \
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add $(BITS_PER_LONG/8), %_ASM_SP; \
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lfence;
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#ifdef __ASSEMBLY__
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/*
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* This should be used immediately before an indirect jump/call. It tells
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* objtool the subsequent indirect jump/call is vouched safe for retpoline
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* builds.
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*/
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.macro ANNOTATE_RETPOLINE_SAFE
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.Lannotate_\@:
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.pushsection .discard.retpoline_safe
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_ASM_PTR .Lannotate_\@
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.popsection
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.endm
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/*
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* (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
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* vs RETBleed validation.
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*/
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#define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
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/*
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* Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
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* eventually turn into it's own annotation.
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*/
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.macro ANNOTATE_UNRET_END
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#ifdef CONFIG_DEBUG_ENTRY
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ANNOTATE_RETPOLINE_SAFE
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nop
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#endif
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.endm
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/*
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* Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call
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* to the retpoline thunk with a CS prefix when the register requires
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* a RAX prefix byte to encode. Also see apply_retpolines().
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*/
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.macro __CS_PREFIX reg:req
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.irp rs,r8,r9,r10,r11,r12,r13,r14,r15
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.ifc \reg,\rs
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.byte 0x2e
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.endif
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.endr
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.endm
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/*
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* JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
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* indirect jmp/call which may be susceptible to the Spectre variant 2
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* attack.
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*/
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.macro JMP_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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__CS_PREFIX \reg
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jmp __x86_indirect_thunk_\reg
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#else
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jmp *%\reg
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int3
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#endif
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.endm
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.macro CALL_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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__CS_PREFIX \reg
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call __x86_indirect_thunk_\reg
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#else
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call *%\reg
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#endif
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.endm
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/*
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* A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
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* monstrosity above, manually.
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*/
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.macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
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ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
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__stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
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__stringify(nop;nop;__FILL_ONE_RETURN), \ftr2
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.Lskip_rsb_\@:
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.endm
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#ifdef CONFIG_CPU_UNRET_ENTRY
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#define CALL_ZEN_UNTRAIN_RET "call zen_untrain_ret"
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#else
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#define CALL_ZEN_UNTRAIN_RET ""
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#endif
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
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* return thunk isn't mapped into the userspace tables (then again, AMD
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* typically has NO_MELTDOWN).
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*
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* While zen_untrain_ret() doesn't clobber anything but requires stack,
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* entry_ibpb() will clobber AX, CX, DX.
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*
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* As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
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* where we have a stack but before any RET instruction.
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*/
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.macro UNTRAIN_RET
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#if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) || \
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defined(CONFIG_CALL_DEPTH_TRACKING)
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ANNOTATE_UNRET_END
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ALTERNATIVE_3 "", \
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CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET, \
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"call entry_ibpb", X86_FEATURE_ENTRY_IBPB, \
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__stringify(RESET_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
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#endif
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.endm
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.macro UNTRAIN_RET_FROM_CALL
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#if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) || \
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defined(CONFIG_CALL_DEPTH_TRACKING)
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ANNOTATE_UNRET_END
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ALTERNATIVE_3 "", \
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CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET, \
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"call entry_ibpb", X86_FEATURE_ENTRY_IBPB, \
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__stringify(RESET_CALL_DEPTH_FROM_CALL), X86_FEATURE_CALL_DEPTH
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#endif
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.endm
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.macro CALL_DEPTH_ACCOUNT
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#ifdef CONFIG_CALL_DEPTH_TRACKING
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ALTERNATIVE "", \
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__stringify(ASM_INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
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#endif
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_RETPOLINE_SAFE \
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"999:\n\t" \
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".pushsection .discard.retpoline_safe\n\t" \
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_ASM_PTR " 999b\n\t" \
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".popsection\n\t"
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typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
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extern retpoline_thunk_t __x86_indirect_thunk_array[];
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extern retpoline_thunk_t __x86_indirect_call_thunk_array[];
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extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];
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extern void __x86_return_thunk(void);
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extern void zen_untrain_ret(void);
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extern void entry_ibpb(void);
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#ifdef CONFIG_CALL_THUNKS
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extern void (*x86_return_thunk)(void);
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#else
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#define x86_return_thunk (&__x86_return_thunk)
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#endif
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#ifdef CONFIG_CALL_DEPTH_TRACKING
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extern void __x86_return_skl(void);
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static inline void x86_set_skl_return_thunk(void)
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{
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x86_return_thunk = &__x86_return_skl;
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}
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#define CALL_DEPTH_ACCOUNT \
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ALTERNATIVE("", \
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__stringify(INCREMENT_CALL_DEPTH), \
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X86_FEATURE_CALL_DEPTH)
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#ifdef CONFIG_CALL_THUNKS_DEBUG
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DECLARE_PER_CPU(u64, __x86_call_count);
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DECLARE_PER_CPU(u64, __x86_ret_count);
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DECLARE_PER_CPU(u64, __x86_stuffs_count);
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DECLARE_PER_CPU(u64, __x86_ctxsw_count);
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#endif
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#else
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||
|
|
static inline void x86_set_skl_return_thunk(void) {}
|
||
|
|
|
||
|
|
#define CALL_DEPTH_ACCOUNT ""
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_RETPOLINE
|
||
|
|
|
||
|
|
#define GEN(reg) \
|
||
|
|
extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
|
||
|
|
#include <asm/GEN-for-each-reg.h>
|
||
|
|
#undef GEN
|
||
|
|
|
||
|
|
#define GEN(reg) \
|
||
|
|
extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg;
|
||
|
|
#include <asm/GEN-for-each-reg.h>
|
||
|
|
#undef GEN
|
||
|
|
|
||
|
|
#define GEN(reg) \
|
||
|
|
extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg;
|
||
|
|
#include <asm/GEN-for-each-reg.h>
|
||
|
|
#undef GEN
|
||
|
|
|
||
|
|
#ifdef CONFIG_X86_64
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Inline asm uses the %V modifier which is only in newer GCC
|
||
|
|
* which is ensured when CONFIG_RETPOLINE is defined.
|
||
|
|
*/
|
||
|
|
# define CALL_NOSPEC \
|
||
|
|
ALTERNATIVE_2( \
|
||
|
|
ANNOTATE_RETPOLINE_SAFE \
|
||
|
|
"call *%[thunk_target]\n", \
|
||
|
|
"call __x86_indirect_thunk_%V[thunk_target]\n", \
|
||
|
|
X86_FEATURE_RETPOLINE, \
|
||
|
|
"lfence;\n" \
|
||
|
|
ANNOTATE_RETPOLINE_SAFE \
|
||
|
|
"call *%[thunk_target]\n", \
|
||
|
|
X86_FEATURE_RETPOLINE_LFENCE)
|
||
|
|
|
||
|
|
# define THUNK_TARGET(addr) [thunk_target] "r" (addr)
|
||
|
|
|
||
|
|
#else /* CONFIG_X86_32 */
|
||
|
|
/*
|
||
|
|
* For i386 we use the original ret-equivalent retpoline, because
|
||
|
|
* otherwise we'll run out of registers. We don't care about CET
|
||
|
|
* here, anyway.
|
||
|
|
*/
|
||
|
|
# define CALL_NOSPEC \
|
||
|
|
ALTERNATIVE_2( \
|
||
|
|
ANNOTATE_RETPOLINE_SAFE \
|
||
|
|
"call *%[thunk_target]\n", \
|
||
|
|
" jmp 904f;\n" \
|
||
|
|
" .align 16\n" \
|
||
|
|
"901: call 903f;\n" \
|
||
|
|
"902: pause;\n" \
|
||
|
|
" lfence;\n" \
|
||
|
|
" jmp 902b;\n" \
|
||
|
|
" .align 16\n" \
|
||
|
|
"903: lea 4(%%esp), %%esp;\n" \
|
||
|
|
" pushl %[thunk_target];\n" \
|
||
|
|
" ret;\n" \
|
||
|
|
" .align 16\n" \
|
||
|
|
"904: call 901b;\n", \
|
||
|
|
X86_FEATURE_RETPOLINE, \
|
||
|
|
"lfence;\n" \
|
||
|
|
ANNOTATE_RETPOLINE_SAFE \
|
||
|
|
"call *%[thunk_target]\n", \
|
||
|
|
X86_FEATURE_RETPOLINE_LFENCE)
|
||
|
|
|
||
|
|
# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
|
||
|
|
#endif
|
||
|
|
#else /* No retpoline for C / inline asm */
|
||
|
|
# define CALL_NOSPEC "call *%[thunk_target]\n"
|
||
|
|
# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* The Spectre V2 mitigation variants */
|
||
|
|
enum spectre_v2_mitigation {
|
||
|
|
SPECTRE_V2_NONE,
|
||
|
|
SPECTRE_V2_RETPOLINE,
|
||
|
|
SPECTRE_V2_LFENCE,
|
||
|
|
SPECTRE_V2_EIBRS,
|
||
|
|
SPECTRE_V2_EIBRS_RETPOLINE,
|
||
|
|
SPECTRE_V2_EIBRS_LFENCE,
|
||
|
|
SPECTRE_V2_IBRS,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* The indirect branch speculation control variants */
|
||
|
|
enum spectre_v2_user_mitigation {
|
||
|
|
SPECTRE_V2_USER_NONE,
|
||
|
|
SPECTRE_V2_USER_STRICT,
|
||
|
|
SPECTRE_V2_USER_STRICT_PREFERRED,
|
||
|
|
SPECTRE_V2_USER_PRCTL,
|
||
|
|
SPECTRE_V2_USER_SECCOMP,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* The Speculative Store Bypass disable variants */
|
||
|
|
enum ssb_mitigation {
|
||
|
|
SPEC_STORE_BYPASS_NONE,
|
||
|
|
SPEC_STORE_BYPASS_DISABLE,
|
||
|
|
SPEC_STORE_BYPASS_PRCTL,
|
||
|
|
SPEC_STORE_BYPASS_SECCOMP,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern char __indirect_thunk_start[];
|
||
|
|
extern char __indirect_thunk_end[];
|
||
|
|
|
||
|
|
static __always_inline
|
||
|
|
void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
|
||
|
|
{
|
||
|
|
asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
|
||
|
|
: : "c" (msr),
|
||
|
|
"a" ((u32)val),
|
||
|
|
"d" ((u32)(val >> 32)),
|
||
|
|
[feature] "i" (feature)
|
||
|
|
: "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void indirect_branch_prediction_barrier(void)
|
||
|
|
{
|
||
|
|
u64 val = PRED_CMD_IBPB;
|
||
|
|
|
||
|
|
alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* The Intel SPEC CTRL MSR base value cache */
|
||
|
|
extern u64 x86_spec_ctrl_base;
|
||
|
|
DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
|
||
|
|
extern void update_spec_ctrl_cond(u64 val);
|
||
|
|
extern u64 spec_ctrl_current(void);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* With retpoline, we must use IBRS to restrict branch prediction
|
||
|
|
* before calling into firmware.
|
||
|
|
*
|
||
|
|
* (Implemented as CPP macros due to header hell.)
|
||
|
|
*/
|
||
|
|
#define firmware_restrict_branch_speculation_start() \
|
||
|
|
do { \
|
||
|
|
preempt_disable(); \
|
||
|
|
alternative_msr_write(MSR_IA32_SPEC_CTRL, \
|
||
|
|
spec_ctrl_current() | SPEC_CTRL_IBRS, \
|
||
|
|
X86_FEATURE_USE_IBRS_FW); \
|
||
|
|
alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
|
||
|
|
X86_FEATURE_USE_IBPB_FW); \
|
||
|
|
} while (0)
|
||
|
|
|
||
|
|
#define firmware_restrict_branch_speculation_end() \
|
||
|
|
do { \
|
||
|
|
alternative_msr_write(MSR_IA32_SPEC_CTRL, \
|
||
|
|
spec_ctrl_current(), \
|
||
|
|
X86_FEATURE_USE_IBRS_FW); \
|
||
|
|
preempt_enable(); \
|
||
|
|
} while (0)
|
||
|
|
|
||
|
|
DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
|
||
|
|
DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
|
||
|
|
DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
|
||
|
|
|
||
|
|
DECLARE_STATIC_KEY_FALSE(mds_user_clear);
|
||
|
|
DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
|
||
|
|
|
||
|
|
DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
|
||
|
|
|
||
|
|
DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
|
||
|
|
|
||
|
|
#include <asm/segment.h>
|
||
|
|
|
||
|
|
/**
|
||
|
|
* mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
|
||
|
|
*
|
||
|
|
* This uses the otherwise unused and obsolete VERW instruction in
|
||
|
|
* combination with microcode which triggers a CPU buffer flush when the
|
||
|
|
* instruction is executed.
|
||
|
|
*/
|
||
|
|
static __always_inline void mds_clear_cpu_buffers(void)
|
||
|
|
{
|
||
|
|
static const u16 ds = __KERNEL_DS;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Has to be the memory-operand variant because only that
|
||
|
|
* guarantees the CPU buffer flush functionality according to
|
||
|
|
* documentation. The register-operand variant does not.
|
||
|
|
* Works with any segment selector, but a valid writable
|
||
|
|
* data segment is the fastest variant.
|
||
|
|
*
|
||
|
|
* "cc" clobber is required because VERW modifies ZF.
|
||
|
|
*/
|
||
|
|
asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
|
||
|
|
*
|
||
|
|
* Clear CPU buffers if the corresponding static key is enabled
|
||
|
|
*/
|
||
|
|
static __always_inline void mds_user_clear_cpu_buffers(void)
|
||
|
|
{
|
||
|
|
if (static_branch_likely(&mds_user_clear))
|
||
|
|
mds_clear_cpu_buffers();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
|
||
|
|
*
|
||
|
|
* Clear CPU buffers if the corresponding static key is enabled
|
||
|
|
*/
|
||
|
|
static __always_inline void mds_idle_clear_cpu_buffers(void)
|
||
|
|
{
|
||
|
|
if (static_branch_likely(&mds_idle_clear))
|
||
|
|
mds_clear_cpu_buffers();
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __ASSEMBLY__ */
|
||
|
|
|
||
|
|
#endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
|