132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PGTABLE_2LEVEL_H
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#define _ASM_X86_PGTABLE_2LEVEL_H
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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static inline void native_set_pte(pte_t *ptep , pte_t pte)
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{
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*ptep = pte;
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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static inline void native_pmd_clear(pmd_t *pmdp)
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{
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native_set_pmd(pmdp, __pmd(0));
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}
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static inline void native_pud_clear(pud_t *pudp)
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{
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}
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static inline void native_pte_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *xp)
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{
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*xp = native_make_pte(0);
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}
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#ifdef CONFIG_SMP
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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{
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return __pte(xchg(&xp->pte_low, 0));
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}
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#endif
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#ifdef CONFIG_SMP
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
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{
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return __pmd(xchg((pmdval_t *)xp, 0));
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}
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#else
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#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
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#endif
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#ifdef CONFIG_SMP
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static inline pud_t native_pudp_get_and_clear(pud_t *xp)
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{
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return __pud(xchg((pudval_t *)xp, 0));
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}
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#else
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#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
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#endif
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/* Bit manipulation helper on pte/pgoff entry */
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static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshift,
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unsigned long mask, unsigned int leftshift)
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{
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return ((value >> rightshift) & mask) << leftshift;
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}
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/*
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* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
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* are !pte_none() && !pte_present().
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*
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* Format of swap PTEs:
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <----------------- offset ------------------> 0 E <- type --> 0
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*
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* E is the exclusive marker that is not stored in swap entries.
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*/
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#define SWP_TYPE_BITS 5
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#define _SWP_TYPE_MASK ((1U << SWP_TYPE_BITS) - 1)
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#define _SWP_TYPE_SHIFT (_PAGE_BIT_PRESENT + 1)
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#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1)
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
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#define __swp_type(x) (((x).val >> _SWP_TYPE_SHIFT) \
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& _SWP_TYPE_MASK)
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#define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) { \
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(((type) & _SWP_TYPE_MASK) << _SWP_TYPE_SHIFT) \
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| ((offset) << SWP_OFFSET_SHIFT) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
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#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
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/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE _PAGE_PSE
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/* No inverted PFNs on 2 level page tables */
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static inline u64 protnone_mask(u64 val)
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{
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return 0;
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}
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static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
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{
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return val;
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}
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static inline bool __pte_needs_invert(u64 val)
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{
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return false;
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}
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#endif /* _ASM_X86_PGTABLE_2LEVEL_H */
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