522 lines
15 KiB
C
522 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Shared support code for AMD K8 northbridges and derivatives.
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* Copyright 2006 Andi Kleen, SUSE Labs.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/spinlock.h>
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#include <linux/pci_ids.h>
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#include <asm/amd_nb.h>
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#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
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#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
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#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
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#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
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#define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
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#define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
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#define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
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#define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
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#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
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#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
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#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
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#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
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#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
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#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
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#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
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#define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
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#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
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#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
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#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
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#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
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#define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
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/* Protect the PCI config register pairs used for SMN. */
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static DEFINE_MUTEX(smn_mutex);
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static u32 *flush_words;
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static const struct pci_device_id amd_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
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{}
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};
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#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
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static const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
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{}
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};
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static const struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
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{}
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};
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static const struct pci_device_id hygon_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
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{}
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};
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static const struct pci_device_id hygon_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{}
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};
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static const struct pci_device_id hygon_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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{}
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};
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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{ 0xfe, 0x00, 0x20 },
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{ }
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};
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static struct amd_northbridge_info amd_northbridges;
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u16 amd_nb_num(void)
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{
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return amd_northbridges.num;
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}
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EXPORT_SYMBOL_GPL(amd_nb_num);
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bool amd_nb_has_feature(unsigned int feature)
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{
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return ((amd_northbridges.flags & feature) == feature);
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}
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EXPORT_SYMBOL_GPL(amd_nb_has_feature);
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struct amd_northbridge *node_to_amd_nb(int node)
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{
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return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
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}
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EXPORT_SYMBOL_GPL(node_to_amd_nb);
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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const struct pci_device_id *ids)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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} while (!pci_match_id(ids, dev));
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return dev;
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}
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static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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{
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struct pci_dev *root;
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int err = -ENODEV;
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if (node >= amd_northbridges.num)
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goto out;
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root = node_to_amd_nb(node)->root;
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if (!root)
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goto out;
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mutex_lock(&smn_mutex);
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err = pci_write_config_dword(root, 0x60, address);
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if (err) {
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pr_warn("Error programming SMN address 0x%x.\n", address);
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goto out_unlock;
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}
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err = (write ? pci_write_config_dword(root, 0x64, *value)
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: pci_read_config_dword(root, 0x64, value));
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if (err)
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pr_warn("Error %s SMN address 0x%x.\n",
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(write ? "writing to" : "reading from"), address);
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out_unlock:
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mutex_unlock(&smn_mutex);
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out:
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return err;
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}
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int amd_smn_read(u16 node, u32 address, u32 *value)
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{
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return __amd_smn_rw(node, address, value, false);
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}
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EXPORT_SYMBOL_GPL(amd_smn_read);
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int amd_smn_write(u16 node, u32 address, u32 value)
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{
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return __amd_smn_rw(node, address, &value, true);
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}
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EXPORT_SYMBOL_GPL(amd_smn_write);
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static int amd_cache_northbridges(void)
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{
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const struct pci_device_id *misc_ids = amd_nb_misc_ids;
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const struct pci_device_id *link_ids = amd_nb_link_ids;
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const struct pci_device_id *root_ids = amd_root_ids;
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struct pci_dev *root, *misc, *link;
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struct amd_northbridge *nb;
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u16 roots_per_misc = 0;
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u16 misc_count = 0;
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u16 root_count = 0;
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u16 i, j;
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if (amd_northbridges.num)
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return 0;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
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root_ids = hygon_root_ids;
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misc_ids = hygon_nb_misc_ids;
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link_ids = hygon_nb_link_ids;
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}
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misc = NULL;
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while ((misc = next_northbridge(misc, misc_ids)))
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misc_count++;
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if (!misc_count)
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return -ENODEV;
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root = NULL;
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while ((root = next_northbridge(root, root_ids)))
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root_count++;
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if (root_count) {
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roots_per_misc = root_count / misc_count;
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/*
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* There should be _exactly_ N roots for each DF/SMN
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* interface.
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*/
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if (!roots_per_misc || (root_count % roots_per_misc)) {
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pr_info("Unsupported AMD DF/PCI configuration found\n");
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return -ENODEV;
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}
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}
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nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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return -ENOMEM;
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amd_northbridges.nb = nb;
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amd_northbridges.num = misc_count;
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link = misc = root = NULL;
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for (i = 0; i < amd_northbridges.num; i++) {
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node_to_amd_nb(i)->root = root =
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next_northbridge(root, root_ids);
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, misc_ids);
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, link_ids);
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/*
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* If there are more PCI root devices than data fabric/
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* system management network interfaces, then the (N)
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* PCI roots per DF/SMN interface are functionally the
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* same (for DF/SMN access) and N-1 are redundant. N-1
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* PCI roots should be skipped per DF/SMN interface so
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* the following DF/SMN interfaces get mapped to
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* correct PCI roots.
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*/
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for (j = 1; j < roots_per_misc; j++)
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root = next_northbridge(root, root_ids);
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}
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if (amd_gart_present())
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amd_northbridges.flags |= AMD_NB_GART;
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/*
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* Check for L3 cache presence.
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*/
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if (!cpuid_edx(0x80000006))
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return 0;
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/*
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* Some CPU families support L3 Cache Index Disable. There are some
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* limitations because of E382 and E388 on family 0x10.
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*/
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model >= 0x8 &&
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(boot_cpu_data.x86_model > 0x9 ||
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boot_cpu_data.x86_stepping >= 0x1))
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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/* L3 cache partitioning is supported on family 0x15 */
|
||
|
|
if (boot_cpu_data.x86 == 0x15)
|
||
|
|
amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Ignores subdevice/subvendor but as far as I can figure out
|
||
|
|
* they're useless anyways
|
||
|
|
*/
|
||
|
|
bool __init early_is_amd_nb(u32 device)
|
||
|
|
{
|
||
|
|
const struct pci_device_id *misc_ids = amd_nb_misc_ids;
|
||
|
|
const struct pci_device_id *id;
|
||
|
|
u32 vendor = device & 0xffff;
|
||
|
|
|
||
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
|
||
|
|
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
|
||
|
|
misc_ids = hygon_nb_misc_ids;
|
||
|
|
|
||
|
|
device >>= 16;
|
||
|
|
for (id = misc_ids; id->vendor; id++)
|
||
|
|
if (vendor == id->vendor && device == id->device)
|
||
|
|
return true;
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct resource *amd_get_mmconfig_range(struct resource *res)
|
||
|
|
{
|
||
|
|
u32 address;
|
||
|
|
u64 base, msr;
|
||
|
|
unsigned int segn_busn_bits;
|
||
|
|
|
||
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
|
||
|
|
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
/* assume all cpus from fam10h have mmconfig */
|
||
|
|
if (boot_cpu_data.x86 < 0x10)
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
address = MSR_FAM10H_MMIO_CONF_BASE;
|
||
|
|
rdmsrl(address, msr);
|
||
|
|
|
||
|
|
/* mmconfig is not enabled */
|
||
|
|
if (!(msr & FAM10H_MMIO_CONF_ENABLE))
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
|
||
|
|
|
||
|
|
segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
|
||
|
|
FAM10H_MMIO_CONF_BUSRANGE_MASK;
|
||
|
|
|
||
|
|
res->flags = IORESOURCE_MEM;
|
||
|
|
res->start = base;
|
||
|
|
res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
int amd_get_subcaches(int cpu)
|
||
|
|
{
|
||
|
|
struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
|
||
|
|
unsigned int mask;
|
||
|
|
|
||
|
|
if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
pci_read_config_dword(link, 0x1d4, &mask);
|
||
|
|
|
||
|
|
return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
|
||
|
|
}
|
||
|
|
|
||
|
|
int amd_set_subcaches(int cpu, unsigned long mask)
|
||
|
|
{
|
||
|
|
static unsigned int reset, ban;
|
||
|
|
struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
|
||
|
|
unsigned int reg;
|
||
|
|
int cuid;
|
||
|
|
|
||
|
|
if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
/* if necessary, collect reset state of L3 partitioning and BAN mode */
|
||
|
|
if (reset == 0) {
|
||
|
|
pci_read_config_dword(nb->link, 0x1d4, &reset);
|
||
|
|
pci_read_config_dword(nb->misc, 0x1b8, &ban);
|
||
|
|
ban &= 0x180000;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* deactivate BAN mode if any subcaches are to be disabled */
|
||
|
|
if (mask != 0xf) {
|
||
|
|
pci_read_config_dword(nb->misc, 0x1b8, ®);
|
||
|
|
pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
|
||
|
|
}
|
||
|
|
|
||
|
|
cuid = cpu_data(cpu).cpu_core_id;
|
||
|
|
mask <<= 4 * cuid;
|
||
|
|
mask |= (0xf ^ (1 << cuid)) << 26;
|
||
|
|
|
||
|
|
pci_write_config_dword(nb->link, 0x1d4, mask);
|
||
|
|
|
||
|
|
/* reset BAN mode if L3 partitioning returned to reset state */
|
||
|
|
pci_read_config_dword(nb->link, 0x1d4, ®);
|
||
|
|
if (reg == reset) {
|
||
|
|
pci_read_config_dword(nb->misc, 0x1b8, ®);
|
||
|
|
reg &= ~0x180000;
|
||
|
|
pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void amd_cache_gart(void)
|
||
|
|
{
|
||
|
|
u16 i;
|
||
|
|
|
||
|
|
if (!amd_nb_has_feature(AMD_NB_GART))
|
||
|
|
return;
|
||
|
|
|
||
|
|
flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
|
||
|
|
if (!flush_words) {
|
||
|
|
amd_northbridges.flags &= ~AMD_NB_GART;
|
||
|
|
pr_notice("Cannot initialize GART flush words, GART support disabled\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i != amd_northbridges.num; i++)
|
||
|
|
pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
void amd_flush_garts(void)
|
||
|
|
{
|
||
|
|
int flushed, i;
|
||
|
|
unsigned long flags;
|
||
|
|
static DEFINE_SPINLOCK(gart_lock);
|
||
|
|
|
||
|
|
if (!amd_nb_has_feature(AMD_NB_GART))
|
||
|
|
return;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Avoid races between AGP and IOMMU. In theory it's not needed
|
||
|
|
* but I'm not sure if the hardware won't lose flush requests
|
||
|
|
* when another is pending. This whole thing is so expensive anyways
|
||
|
|
* that it doesn't matter to serialize more. -AK
|
||
|
|
*/
|
||
|
|
spin_lock_irqsave(&gart_lock, flags);
|
||
|
|
flushed = 0;
|
||
|
|
for (i = 0; i < amd_northbridges.num; i++) {
|
||
|
|
pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
|
||
|
|
flush_words[i] | 1);
|
||
|
|
flushed++;
|
||
|
|
}
|
||
|
|
for (i = 0; i < amd_northbridges.num; i++) {
|
||
|
|
u32 w;
|
||
|
|
/* Make sure the hardware actually executed the flush*/
|
||
|
|
for (;;) {
|
||
|
|
pci_read_config_dword(node_to_amd_nb(i)->misc,
|
||
|
|
0x9c, &w);
|
||
|
|
if (!(w & 1))
|
||
|
|
break;
|
||
|
|
cpu_relax();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
spin_unlock_irqrestore(&gart_lock, flags);
|
||
|
|
if (!flushed)
|
||
|
|
pr_notice("nothing to flush?\n");
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(amd_flush_garts);
|
||
|
|
|
||
|
|
static void __fix_erratum_688(void *info)
|
||
|
|
{
|
||
|
|
#define MSR_AMD64_IC_CFG 0xC0011021
|
||
|
|
|
||
|
|
msr_set_bit(MSR_AMD64_IC_CFG, 3);
|
||
|
|
msr_set_bit(MSR_AMD64_IC_CFG, 14);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Apply erratum 688 fix so machines without a BIOS fix work. */
|
||
|
|
static __init void fix_erratum_688(void)
|
||
|
|
{
|
||
|
|
struct pci_dev *F4;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
if (boot_cpu_data.x86 != 0x14)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (!amd_northbridges.num)
|
||
|
|
return;
|
||
|
|
|
||
|
|
F4 = node_to_amd_nb(0)->link;
|
||
|
|
if (!F4)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (pci_read_config_dword(F4, 0x164, &val))
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (val & BIT(2))
|
||
|
|
return;
|
||
|
|
|
||
|
|
on_each_cpu(__fix_erratum_688, NULL, 0);
|
||
|
|
|
||
|
|
pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
static __init int init_amd_nbs(void)
|
||
|
|
{
|
||
|
|
amd_cache_northbridges();
|
||
|
|
amd_cache_gart();
|
||
|
|
|
||
|
|
fix_erratum_688();
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This has to go after the PCI subsystem */
|
||
|
|
fs_initcall(init_amd_nbs);
|