67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* P5 specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/smp.h>
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#include <linux/hardirq.h>
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#include <asm/processor.h>
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#include <asm/traps.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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#include "internal.h"
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/* By default disabled */
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int mce_p5_enabled __read_mostly;
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/* Machine check handler for Pentium class Intel CPUs: */
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noinstr void pentium_machine_check(struct pt_regs *regs)
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{
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u32 loaddr, hi, lotype;
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instrumentation_begin();
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rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
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rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
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pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
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smp_processor_id(), loaddr, lotype);
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if (lotype & (1<<5)) {
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pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
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smp_processor_id());
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}
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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instrumentation_end();
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}
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/* Set up machine check reporting for processors with Intel style MCE: */
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/* Default P5 to off as its often misconnected: */
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if (!mce_p5_enabled)
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return;
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/* Check for MCE support: */
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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/* Read registers before enabling: */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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pr_info("Intel old style machine check architecture supported.\n");
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/* Enable MCE: */
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cr4_set_bits(X86_CR4_MCE);
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pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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}
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