280 lines
8.1 KiB
C
280 lines
8.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Intel SMP support routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
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* (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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* (c) 2002,2003 Andi Kleen, SuSE Labs.
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*
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* i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/cache.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/gfp.h>
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#include <asm/mtrr.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/idtentry.h>
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#include <asm/nmi.h>
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#include <asm/mce.h>
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#include <asm/trace/irq_vectors.h>
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#include <asm/kexec.h>
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#include <asm/reboot.h>
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/*
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* Some notes on x86 processor bugs affecting SMP operation:
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*
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* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
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* The Linux implications for SMP are handled as follows:
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*
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* Pentium III / [Xeon]
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* None of the E1AP-E3AP errata are visible to the user.
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*
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* E1AP. see PII A1AP
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* E2AP. see PII A2AP
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* E3AP. see PII A3AP
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*
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* Pentium II / [Xeon]
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* None of the A1AP-A3AP errata are visible to the user.
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*
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* A1AP. see PPro 1AP
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* A2AP. see PPro 2AP
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* A3AP. see PPro 7AP
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*
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* Pentium Pro
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* None of 1AP-9AP errata are visible to the normal user,
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* except occasional delivery of 'spurious interrupt' as trap #15.
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* This is very rare and a non-problem.
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*
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* 1AP. Linux maps APIC as non-cacheable
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* 2AP. worked around in hardware
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* 3AP. fixed in C0 and above steppings microcode update.
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* Linux does not use excessive STARTUP_IPIs.
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* 4AP. worked around in hardware
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* 5AP. symmetric IO mode (normal Linux operation) not affected.
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* 'noapic' mode has vector 0xf filled out properly.
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* 6AP. 'noapic' mode might be affected - fixed in later steppings
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* 7AP. We do not assume writes to the LVT deasserting IRQs
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* 8AP. We do not enable low power mode (deep sleep) during MP bootup
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* 9AP. We do not use mixed mode
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*
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* Pentium
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* There is a marginal case where REP MOVS on 100MHz SMP
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* machines with B stepping processors can fail. XXX should provide
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* an L1cache=Writethrough or L1cache=off option.
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*
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* B stepping CPUs may hang. There are hardware work arounds
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* for this. We warn about it in case your board doesn't have the work
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* arounds. Basically that's so I can tell anyone with a B stepping
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* CPU and SMP problems "tough".
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*
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* Specific items [From Pentium Processor Specification Update]
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*
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* 1AP. Linux doesn't use remote read
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* 2AP. Linux doesn't trust APIC errors
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* 3AP. We work around this
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* 4AP. Linux never generated 3 interrupts of the same priority
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* to cause a lost local interrupt.
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* 5AP. Remote read is never used
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* 6AP. not affected - worked around in hardware
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* 7AP. not affected - worked around in hardware
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* 8AP. worked around in hardware - we get explicit CS errors if not
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* 9AP. only 'noapic' mode affected. Might generate spurious
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* interrupts, we log only the first one and count the
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* rest silently.
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* 10AP. not affected - worked around in hardware
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* 11AP. Linux reads the APIC between writes to avoid this, as per
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* the documentation. Make sure you preserve this as it affects
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* the C stepping chips too.
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* 12AP. not affected - worked around in hardware
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* 13AP. not affected - worked around in hardware
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* 14AP. we always deassert INIT during bootup
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* 15AP. not affected - worked around in hardware
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* 16AP. not affected - worked around in hardware
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* 17AP. not affected - worked around in hardware
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* 18AP. not affected - worked around in hardware
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* 19AP. not affected - worked around in BIOS
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*
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* If this sounds worrying believe me these bugs are either ___RARE___,
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* or are signal timing bugs worked around in hardware and there's
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* about nothing of note with C stepping upwards.
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*/
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static atomic_t stopping_cpu = ATOMIC_INIT(-1);
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static bool smp_no_nmi_ipi = false;
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static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
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{
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/* We are registered on stopping cpu too, avoid spurious NMI */
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if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
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return NMI_HANDLED;
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cpu_emergency_disable_virtualization();
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stop_this_cpu(NULL);
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return NMI_HANDLED;
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}
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/*
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* this function calls the 'stop' function on all other CPUs in the system.
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*/
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DEFINE_IDTENTRY_SYSVEC(sysvec_reboot)
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{
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ack_APIC_irq();
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cpu_emergency_disable_virtualization();
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stop_this_cpu(NULL);
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}
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static int register_stop_handler(void)
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{
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return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
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NMI_FLAG_FIRST, "smp_stop");
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}
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static void native_stop_other_cpus(int wait)
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{
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unsigned long flags;
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unsigned long timeout;
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if (reboot_force)
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return;
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/*
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* Use an own vector here because smp_call_function
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* does lots of things not suitable in a panic situation.
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*/
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/*
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* We start by using the REBOOT_VECTOR irq.
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* The irq is treated as a sync point to allow critical
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* regions of code on other cpus to release their spin locks
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* and re-enable irqs. Jumping straight to an NMI might
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* accidentally cause deadlocks with further shutdown/panic
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* code. By syncing, we give the cpus up to one second to
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* finish their work before we force them off with the NMI.
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*/
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if (num_online_cpus() > 1) {
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/* did someone beat us here? */
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if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
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return;
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/* sync above data before sending IRQ */
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wmb();
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apic_send_IPI_allbutself(REBOOT_VECTOR);
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/*
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* Don't wait longer than a second for IPI completion. The
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* wait request is not checked here because that would
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* prevent an NMI shutdown attempt in case that not all
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* CPUs reach shutdown state.
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*/
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timeout = USEC_PER_SEC;
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while (num_online_cpus() > 1 && timeout--)
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udelay(1);
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}
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/* if the REBOOT_VECTOR didn't work, try with the NMI */
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if (num_online_cpus() > 1) {
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/*
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* If NMI IPI is enabled, try to register the stop handler
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* and send the IPI. In any case try to wait for the other
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* CPUs to stop.
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*/
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if (!smp_no_nmi_ipi && !register_stop_handler()) {
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/* Sync above data before sending IRQ */
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wmb();
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pr_emerg("Shutting down cpus with NMI\n");
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apic_send_IPI_allbutself(NMI_VECTOR);
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}
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/*
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* Don't wait longer than 10 ms if the caller didn't
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* request it. If wait is true, the machine hangs here if
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* one or more CPUs do not reach shutdown state.
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*/
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timeout = USEC_PER_MSEC * 10;
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while (num_online_cpus() > 1 && (wait || timeout--))
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udelay(1);
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}
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local_irq_save(flags);
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disable_local_APIC();
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mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
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local_irq_restore(flags);
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}
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/*
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* Reschedule call back. KVM uses this interrupt to force a cpu out of
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* guest mode.
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*/
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DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi)
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{
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ack_APIC_irq();
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trace_reschedule_entry(RESCHEDULE_VECTOR);
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inc_irq_stat(irq_resched_count);
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scheduler_ipi();
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trace_reschedule_exit(RESCHEDULE_VECTOR);
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}
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DEFINE_IDTENTRY_SYSVEC(sysvec_call_function)
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{
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ack_APIC_irq();
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trace_call_function_entry(CALL_FUNCTION_VECTOR);
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inc_irq_stat(irq_call_count);
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generic_smp_call_function_interrupt();
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trace_call_function_exit(CALL_FUNCTION_VECTOR);
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}
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DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single)
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{
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ack_APIC_irq();
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trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
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inc_irq_stat(irq_call_count);
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generic_smp_call_function_single_interrupt();
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trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
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}
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static int __init nonmi_ipi_setup(char *str)
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{
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smp_no_nmi_ipi = true;
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return 1;
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}
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__setup("nonmi_ipi", nonmi_ipi_setup);
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struct smp_ops smp_ops = {
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.smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
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.smp_prepare_cpus = native_smp_prepare_cpus,
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.smp_cpus_done = native_smp_cpus_done,
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.stop_other_cpus = native_stop_other_cpus,
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#if defined(CONFIG_KEXEC_CORE)
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.crash_stop_other_cpus = kdump_nmi_shootdown_cpus,
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#endif
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.smp_send_reschedule = native_smp_send_reschedule,
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.cpu_up = native_cpu_up,
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.cpu_die = native_cpu_die,
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.cpu_disable = native_cpu_disable,
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.play_dead = native_play_dead,
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.send_call_func_ipi = native_send_call_func_ipi,
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.send_call_func_single_ipi = native_send_call_func_single_ipi,
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};
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EXPORT_SYMBOL_GPL(smp_ops);
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