139 lines
3.3 KiB
C
139 lines
3.3 KiB
C
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/*
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* arch/xtensa/include/asm/traps.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 Tensilica Inc.
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*/
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#ifndef _XTENSA_TRAPS_H
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#define _XTENSA_TRAPS_H
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#include <asm/ptrace.h>
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typedef void xtensa_exception_handler(struct pt_regs *regs);
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/*
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* Per-CPU exception handling data structure.
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* EXCSAVE1 points to it.
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*/
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struct exc_table {
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/* Kernel Stack */
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void *kstk;
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/* Double exception save area for a0 */
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unsigned long double_save;
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/* Fixup handler */
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void *fixup;
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/* For passing a parameter to fixup */
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void *fixup_param;
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#if XTENSA_HAVE_COPROCESSORS
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/* Pointers to owner struct thread_info */
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struct thread_info *coprocessor_owner[XCHAL_CP_MAX];
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#endif
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/* Fast user exception handlers */
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void *fast_user_handler[EXCCAUSE_N];
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/* Fast kernel exception handlers */
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void *fast_kernel_handler[EXCCAUSE_N];
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/* Default C-Handlers */
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xtensa_exception_handler *default_handler[EXCCAUSE_N];
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};
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DECLARE_PER_CPU(struct exc_table, exc_table);
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xtensa_exception_handler *
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__init trap_set_handler(int cause, xtensa_exception_handler *handler);
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asmlinkage void fast_illegal_instruction_user(void);
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asmlinkage void fast_syscall_user(void);
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asmlinkage void fast_alloca(void);
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asmlinkage void fast_unaligned(void);
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asmlinkage void fast_second_level_miss(void);
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asmlinkage void fast_store_prohibited(void);
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asmlinkage void fast_coprocessor(void);
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asmlinkage void kernel_exception(void);
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asmlinkage void user_exception(void);
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asmlinkage void system_call(struct pt_regs *regs);
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void do_IRQ(int hwirq, struct pt_regs *regs);
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void do_page_fault(struct pt_regs *regs);
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void do_unhandled(struct pt_regs *regs);
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/* Initialize minimal exc_table structure sufficient for basic paging */
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static inline void __init early_trap_init(void)
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{
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static struct exc_table init_exc_table __initdata = {
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.fast_kernel_handler[EXCCAUSE_DTLB_MISS] =
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fast_second_level_miss,
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};
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xtensa_set_sr(&init_exc_table, excsave1);
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}
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void secondary_trap_init(void);
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static inline void spill_registers(void)
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{
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#if defined(__XTENSA_WINDOWED_ABI__)
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#if XCHAL_NUM_AREGS > 16
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__asm__ __volatile__ (
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" call8 1f\n"
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" _j 2f\n"
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" retw\n"
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" .align 4\n"
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"1:\n"
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#if XCHAL_NUM_AREGS == 32
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" _entry a1, 32\n"
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" addi a8, a0, 3\n"
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" _entry a1, 16\n"
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" mov a12, a12\n"
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" retw\n"
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#else
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" _entry a1, 48\n"
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" call12 1f\n"
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" retw\n"
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" .align 4\n"
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"1:\n"
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" .rept (" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
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" _entry a1, 48\n"
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" mov a12, a0\n"
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" .endr\n"
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" _entry a1, 16\n"
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#if XCHAL_NUM_AREGS % 12 == 0
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" mov a12, a12\n"
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#elif XCHAL_NUM_AREGS % 12 == 4
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" mov a4, a4\n"
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#elif XCHAL_NUM_AREGS % 12 == 8
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" mov a8, a8\n"
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#endif
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" retw\n"
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#endif
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"2:\n"
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: : : "a8", "a9", "memory");
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#else
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__asm__ __volatile__ (
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" mov a12, a12\n"
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: : : "memory");
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#endif
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#endif
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}
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struct debug_table {
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/* Pointer to debug exception handler */
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void (*debug_exception)(void);
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/* Temporary register save area */
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unsigned long debug_save[1];
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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/* Save area for DBREAKC registers */
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unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
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/* Saved ICOUNT register */
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unsigned long icount_save;
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/* Saved ICOUNTLEVEL register */
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unsigned long icount_level_save;
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#endif
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};
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void debug_exception(void);
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#endif /* _XTENSA_TRAPS_H */
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