351 lines
9.4 KiB
C
351 lines
9.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/edac.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include "edac_module.h"
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/* Registers Offset */
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#define AL_MC_ECC_CFG 0x70
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#define AL_MC_ECC_CLEAR 0x7c
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#define AL_MC_ECC_ERR_COUNT 0x80
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#define AL_MC_ECC_CE_ADDR0 0x84
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#define AL_MC_ECC_CE_ADDR1 0x88
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#define AL_MC_ECC_UE_ADDR0 0xa4
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#define AL_MC_ECC_UE_ADDR1 0xa8
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#define AL_MC_ECC_CE_SYND0 0x8c
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#define AL_MC_ECC_CE_SYND1 0x90
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#define AL_MC_ECC_CE_SYND2 0x94
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#define AL_MC_ECC_UE_SYND0 0xac
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#define AL_MC_ECC_UE_SYND1 0xb0
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#define AL_MC_ECC_UE_SYND2 0xb4
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/* Registers Fields */
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#define AL_MC_ECC_CFG_SCRUB_DISABLED BIT(4)
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#define AL_MC_ECC_CLEAR_UE_COUNT BIT(3)
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#define AL_MC_ECC_CLEAR_CE_COUNT BIT(2)
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#define AL_MC_ECC_CLEAR_UE_ERR BIT(1)
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#define AL_MC_ECC_CLEAR_CE_ERR BIT(0)
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#define AL_MC_ECC_ERR_COUNT_UE GENMASK(31, 16)
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#define AL_MC_ECC_ERR_COUNT_CE GENMASK(15, 0)
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#define AL_MC_ECC_CE_ADDR0_RANK GENMASK(25, 24)
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#define AL_MC_ECC_CE_ADDR0_ROW GENMASK(17, 0)
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#define AL_MC_ECC_CE_ADDR1_BG GENMASK(25, 24)
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#define AL_MC_ECC_CE_ADDR1_BANK GENMASK(18, 16)
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#define AL_MC_ECC_CE_ADDR1_COLUMN GENMASK(11, 0)
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#define AL_MC_ECC_UE_ADDR0_RANK GENMASK(25, 24)
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#define AL_MC_ECC_UE_ADDR0_ROW GENMASK(17, 0)
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#define AL_MC_ECC_UE_ADDR1_BG GENMASK(25, 24)
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#define AL_MC_ECC_UE_ADDR1_BANK GENMASK(18, 16)
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#define AL_MC_ECC_UE_ADDR1_COLUMN GENMASK(11, 0)
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#define DRV_NAME "al_mc_edac"
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#define AL_MC_EDAC_MSG_MAX 256
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struct al_mc_edac {
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void __iomem *mmio_base;
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spinlock_t lock;
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int irq_ce;
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int irq_ue;
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};
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static void prepare_msg(char *message, size_t buffer_size,
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enum hw_event_mc_err_type type,
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u8 rank, u32 row, u8 bg, u8 bank, u16 column,
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u32 syn0, u32 syn1, u32 syn2)
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{
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snprintf(message, buffer_size,
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"%s rank=0x%x row=0x%x bg=0x%x bank=0x%x col=0x%x syn0: 0x%x syn1: 0x%x syn2: 0x%x",
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type == HW_EVENT_ERR_UNCORRECTED ? "UE" : "CE",
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rank, row, bg, bank, column, syn0, syn1, syn2);
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}
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static int handle_ce(struct mem_ctl_info *mci)
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{
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u32 eccerrcnt, ecccaddr0, ecccaddr1, ecccsyn0, ecccsyn1, ecccsyn2, row;
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struct al_mc_edac *al_mc = mci->pvt_info;
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char msg[AL_MC_EDAC_MSG_MAX];
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u16 ce_count, column;
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unsigned long flags;
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u8 rank, bg, bank;
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eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT);
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ce_count = FIELD_GET(AL_MC_ECC_ERR_COUNT_CE, eccerrcnt);
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if (!ce_count)
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return 0;
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ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0);
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ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1);
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ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0);
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ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1);
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ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2);
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writel_relaxed(AL_MC_ECC_CLEAR_CE_COUNT | AL_MC_ECC_CLEAR_CE_ERR,
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al_mc->mmio_base + AL_MC_ECC_CLEAR);
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dev_dbg(mci->pdev, "eccuaddr0=0x%08x eccuaddr1=0x%08x\n",
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ecccaddr0, ecccaddr1);
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rank = FIELD_GET(AL_MC_ECC_CE_ADDR0_RANK, ecccaddr0);
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row = FIELD_GET(AL_MC_ECC_CE_ADDR0_ROW, ecccaddr0);
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bg = FIELD_GET(AL_MC_ECC_CE_ADDR1_BG, ecccaddr1);
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bank = FIELD_GET(AL_MC_ECC_CE_ADDR1_BANK, ecccaddr1);
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column = FIELD_GET(AL_MC_ECC_CE_ADDR1_COLUMN, ecccaddr1);
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prepare_msg(msg, sizeof(msg), HW_EVENT_ERR_CORRECTED,
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rank, row, bg, bank, column,
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ecccsyn0, ecccsyn1, ecccsyn2);
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spin_lock_irqsave(&al_mc->lock, flags);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
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ce_count, 0, 0, 0, 0, 0, -1, mci->ctl_name, msg);
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spin_unlock_irqrestore(&al_mc->lock, flags);
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return ce_count;
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}
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static int handle_ue(struct mem_ctl_info *mci)
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{
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u32 eccerrcnt, eccuaddr0, eccuaddr1, eccusyn0, eccusyn1, eccusyn2, row;
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struct al_mc_edac *al_mc = mci->pvt_info;
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char msg[AL_MC_EDAC_MSG_MAX];
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u16 ue_count, column;
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unsigned long flags;
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u8 rank, bg, bank;
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eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT);
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ue_count = FIELD_GET(AL_MC_ECC_ERR_COUNT_UE, eccerrcnt);
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if (!ue_count)
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return 0;
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eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0);
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eccuaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR1);
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eccusyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND0);
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eccusyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND1);
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eccusyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND2);
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writel_relaxed(AL_MC_ECC_CLEAR_UE_COUNT | AL_MC_ECC_CLEAR_UE_ERR,
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al_mc->mmio_base + AL_MC_ECC_CLEAR);
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dev_dbg(mci->pdev, "eccuaddr0=0x%08x eccuaddr1=0x%08x\n",
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eccuaddr0, eccuaddr1);
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rank = FIELD_GET(AL_MC_ECC_UE_ADDR0_RANK, eccuaddr0);
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row = FIELD_GET(AL_MC_ECC_UE_ADDR0_ROW, eccuaddr0);
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bg = FIELD_GET(AL_MC_ECC_UE_ADDR1_BG, eccuaddr1);
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bank = FIELD_GET(AL_MC_ECC_UE_ADDR1_BANK, eccuaddr1);
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column = FIELD_GET(AL_MC_ECC_UE_ADDR1_COLUMN, eccuaddr1);
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prepare_msg(msg, sizeof(msg), HW_EVENT_ERR_UNCORRECTED,
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rank, row, bg, bank, column,
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eccusyn0, eccusyn1, eccusyn2);
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spin_lock_irqsave(&al_mc->lock, flags);
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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ue_count, 0, 0, 0, 0, 0, -1, mci->ctl_name, msg);
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spin_unlock_irqrestore(&al_mc->lock, flags);
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return ue_count;
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}
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static void al_mc_edac_check(struct mem_ctl_info *mci)
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{
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struct al_mc_edac *al_mc = mci->pvt_info;
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if (al_mc->irq_ue <= 0)
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handle_ue(mci);
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if (al_mc->irq_ce <= 0)
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handle_ce(mci);
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}
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static irqreturn_t al_mc_edac_irq_handler_ue(int irq, void *info)
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{
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struct platform_device *pdev = info;
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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if (handle_ue(mci))
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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static irqreturn_t al_mc_edac_irq_handler_ce(int irq, void *info)
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{
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struct platform_device *pdev = info;
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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if (handle_ce(mci))
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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static enum scrub_type get_scrub_mode(void __iomem *mmio_base)
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{
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u32 ecccfg0;
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ecccfg0 = readl(mmio_base + AL_MC_ECC_CFG);
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if (FIELD_GET(AL_MC_ECC_CFG_SCRUB_DISABLED, ecccfg0))
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return SCRUB_NONE;
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else
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return SCRUB_HW_SRC;
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}
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static void devm_al_mc_edac_free(void *data)
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{
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edac_mc_free(data);
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}
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static void devm_al_mc_edac_del(void *data)
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{
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edac_mc_del_mc(data);
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}
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static int al_mc_edac_probe(struct platform_device *pdev)
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{
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struct edac_mc_layer layers[1];
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struct mem_ctl_info *mci;
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struct al_mc_edac *al_mc;
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void __iomem *mmio_base;
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struct dimm_info *dimm;
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int ret;
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mmio_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mmio_base)) {
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dev_err(&pdev->dev, "failed to ioremap memory (%ld)\n",
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PTR_ERR(mmio_base));
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return PTR_ERR(mmio_base);
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}
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = 1;
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layers[0].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct al_mc_edac));
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if (!mci)
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return -ENOMEM;
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ret = devm_add_action_or_reset(&pdev->dev, devm_al_mc_edac_free, mci);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, mci);
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al_mc = mci->pvt_info;
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al_mc->mmio_base = mmio_base;
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al_mc->irq_ue = of_irq_get_byname(pdev->dev.of_node, "ue");
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if (al_mc->irq_ue <= 0)
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dev_dbg(&pdev->dev,
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"no IRQ defined for UE - falling back to polling\n");
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al_mc->irq_ce = of_irq_get_byname(pdev->dev.of_node, "ce");
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if (al_mc->irq_ce <= 0)
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dev_dbg(&pdev->dev,
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"no IRQ defined for CE - falling back to polling\n");
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/*
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* In case both interrupts (ue/ce) are to be found, use interrupt mode.
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* In case none of the interrupt are foud, use polling mode.
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* In case only one interrupt is found, use interrupt mode for it but
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* keep polling mode enable for the other.
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*/
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if (al_mc->irq_ue <= 0 || al_mc->irq_ce <= 0) {
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edac_op_state = EDAC_OPSTATE_POLL;
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mci->edac_check = al_mc_edac_check;
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} else {
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edac_op_state = EDAC_OPSTATE_INT;
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}
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spin_lock_init(&al_mc->lock);
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mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = DRV_NAME;
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mci->ctl_name = "al_mc";
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mci->pdev = &pdev->dev;
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mci->scrub_mode = get_scrub_mode(mmio_base);
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dimm = *mci->dimms;
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dimm->grain = 1;
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ret = edac_mc_add_mc(mci);
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if (ret < 0) {
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dev_err(&pdev->dev,
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"fail to add memory controller device (%d)\n",
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ret);
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return ret;
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}
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ret = devm_add_action_or_reset(&pdev->dev, devm_al_mc_edac_del, &pdev->dev);
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if (ret)
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return ret;
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if (al_mc->irq_ue > 0) {
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ret = devm_request_irq(&pdev->dev,
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al_mc->irq_ue,
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al_mc_edac_irq_handler_ue,
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IRQF_SHARED,
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pdev->name,
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pdev);
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if (ret != 0) {
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dev_err(&pdev->dev,
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"failed to request UE IRQ %d (%d)\n",
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al_mc->irq_ue, ret);
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return ret;
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}
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}
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if (al_mc->irq_ce > 0) {
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ret = devm_request_irq(&pdev->dev,
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al_mc->irq_ce,
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al_mc_edac_irq_handler_ce,
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IRQF_SHARED,
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pdev->name,
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pdev);
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if (ret != 0) {
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dev_err(&pdev->dev,
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"failed to request CE IRQ %d (%d)\n",
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al_mc->irq_ce, ret);
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return ret;
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}
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||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id al_mc_edac_of_match[] = {
|
||
|
|
{ .compatible = "amazon,al-mc-edac", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_DEVICE_TABLE(of, al_mc_edac_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver al_mc_edac_driver = {
|
||
|
|
.probe = al_mc_edac_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = DRV_NAME,
|
||
|
|
.of_match_table = al_mc_edac_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(al_mc_edac_driver);
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_AUTHOR("Talel Shenhar");
|
||
|
|
MODULE_DESCRIPTION("Amazon's Annapurna Lab's Memory Controller EDAC Driver");
|