325 lines
8.5 KiB
C
325 lines
8.5 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*
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* Copyright (c) 2013 by Cisco Systems, Inc.
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* All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/edac.h>
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#include <linux/ctype.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-lmcx-defs.h>
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#include "edac_module.h"
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#define OCTEON_MAX_MC 4
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#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
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struct octeon_lmc_pvt {
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unsigned long inject;
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unsigned long error_type;
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unsigned long dimm;
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unsigned long rank;
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unsigned long bank;
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unsigned long row;
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unsigned long col;
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};
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static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
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{
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union cvmx_lmcx_mem_cfg0 cfg0;
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bool do_clear = false;
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char msg[64];
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cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx));
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if (cfg0.s.sec_err || cfg0.s.ded_err) {
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union cvmx_lmcx_fadr fadr;
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fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
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snprintf(msg, sizeof(msg),
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"DIMM %d rank %d bank %d row %d col %d",
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fadr.cn30xx.fdimm, fadr.cn30xx.fbunk,
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fadr.cn30xx.fbank, fadr.cn30xx.frow, fadr.cn30xx.fcol);
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}
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if (cfg0.s.sec_err) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
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-1, -1, -1, msg, "");
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cfg0.s.sec_err = -1; /* Done, re-arm */
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do_clear = true;
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}
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if (cfg0.s.ded_err) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
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-1, -1, -1, msg, "");
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cfg0.s.ded_err = -1; /* Done, re-arm */
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do_clear = true;
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}
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if (do_clear)
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cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64);
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}
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static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
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{
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struct octeon_lmc_pvt *pvt = mci->pvt_info;
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union cvmx_lmcx_int int_reg;
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bool do_clear = false;
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char msg[64];
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if (!pvt->inject)
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int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
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else {
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int_reg.u64 = 0;
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if (pvt->error_type == 1)
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int_reg.s.sec_err = 1;
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if (pvt->error_type == 2)
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int_reg.s.ded_err = 1;
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}
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if (int_reg.s.sec_err || int_reg.s.ded_err) {
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union cvmx_lmcx_fadr fadr;
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if (likely(!pvt->inject))
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fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
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else {
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fadr.cn61xx.fdimm = pvt->dimm;
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fadr.cn61xx.fbunk = pvt->rank;
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fadr.cn61xx.fbank = pvt->bank;
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fadr.cn61xx.frow = pvt->row;
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fadr.cn61xx.fcol = pvt->col;
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}
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snprintf(msg, sizeof(msg),
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"DIMM %d rank %d bank %d row %d col %d",
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fadr.cn61xx.fdimm, fadr.cn61xx.fbunk,
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fadr.cn61xx.fbank, fadr.cn61xx.frow, fadr.cn61xx.fcol);
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}
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if (int_reg.s.sec_err) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
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-1, -1, -1, msg, "");
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int_reg.s.sec_err = -1; /* Done, re-arm */
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do_clear = true;
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}
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if (int_reg.s.ded_err) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
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-1, -1, -1, msg, "");
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int_reg.s.ded_err = -1; /* Done, re-arm */
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do_clear = true;
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}
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if (do_clear) {
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if (likely(!pvt->inject))
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cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
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else
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pvt->inject = 0;
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}
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}
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/************************ MC SYSFS parts ***********************************/
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/* Only a couple naming differences per template, so very similar */
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#define TEMPLATE_SHOW(reg) \
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static ssize_t octeon_mc_inject_##reg##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *data) \
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{ \
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struct mem_ctl_info *mci = to_mci(dev); \
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struct octeon_lmc_pvt *pvt = mci->pvt_info; \
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return sprintf(data, "%016llu\n", (u64)pvt->reg); \
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}
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#define TEMPLATE_STORE(reg) \
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static ssize_t octeon_mc_inject_##reg##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *data, size_t count) \
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{ \
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struct mem_ctl_info *mci = to_mci(dev); \
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struct octeon_lmc_pvt *pvt = mci->pvt_info; \
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if (isdigit(*data)) { \
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if (!kstrtoul(data, 0, &pvt->reg)) \
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return count; \
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} \
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return 0; \
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}
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TEMPLATE_SHOW(inject);
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TEMPLATE_STORE(inject);
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TEMPLATE_SHOW(dimm);
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TEMPLATE_STORE(dimm);
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TEMPLATE_SHOW(bank);
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TEMPLATE_STORE(bank);
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TEMPLATE_SHOW(rank);
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TEMPLATE_STORE(rank);
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TEMPLATE_SHOW(row);
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TEMPLATE_STORE(row);
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TEMPLATE_SHOW(col);
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TEMPLATE_STORE(col);
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static ssize_t octeon_mc_inject_error_type_store(struct device *dev,
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struct device_attribute *attr,
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const char *data,
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size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct octeon_lmc_pvt *pvt = mci->pvt_info;
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if (!strncmp(data, "single", 6))
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pvt->error_type = 1;
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else if (!strncmp(data, "double", 6))
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pvt->error_type = 2;
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return count;
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}
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static ssize_t octeon_mc_inject_error_type_show(struct device *dev,
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struct device_attribute *attr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct octeon_lmc_pvt *pvt = mci->pvt_info;
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if (pvt->error_type == 1)
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return sprintf(data, "single");
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else if (pvt->error_type == 2)
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return sprintf(data, "double");
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return 0;
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}
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static DEVICE_ATTR(inject, S_IRUGO | S_IWUSR,
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octeon_mc_inject_inject_show, octeon_mc_inject_inject_store);
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static DEVICE_ATTR(error_type, S_IRUGO | S_IWUSR,
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octeon_mc_inject_error_type_show, octeon_mc_inject_error_type_store);
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static DEVICE_ATTR(dimm, S_IRUGO | S_IWUSR,
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octeon_mc_inject_dimm_show, octeon_mc_inject_dimm_store);
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static DEVICE_ATTR(rank, S_IRUGO | S_IWUSR,
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octeon_mc_inject_rank_show, octeon_mc_inject_rank_store);
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static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,
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octeon_mc_inject_bank_show, octeon_mc_inject_bank_store);
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static DEVICE_ATTR(row, S_IRUGO | S_IWUSR,
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octeon_mc_inject_row_show, octeon_mc_inject_row_store);
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static DEVICE_ATTR(col, S_IRUGO | S_IWUSR,
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octeon_mc_inject_col_show, octeon_mc_inject_col_store);
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static struct attribute *octeon_dev_attrs[] = {
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&dev_attr_inject.attr,
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&dev_attr_error_type.attr,
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&dev_attr_dimm.attr,
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&dev_attr_rank.attr,
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&dev_attr_bank.attr,
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&dev_attr_row.attr,
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&dev_attr_col.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(octeon_dev);
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static int octeon_lmc_edac_probe(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[1];
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int mc = pdev->id;
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opstate_init();
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layers[0].type = EDAC_MC_LAYER_CHANNEL;
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layers[0].size = 1;
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layers[0].is_virt_csrow = false;
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if (OCTEON_IS_OCTEON1PLUS()) {
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union cvmx_lmcx_mem_cfg0 cfg0;
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cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
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if (!cfg0.s.ecc_ena) {
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dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
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return 0;
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}
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mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
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if (!mci)
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return -ENXIO;
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mci->pdev = &pdev->dev;
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mci->dev_name = dev_name(&pdev->dev);
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mci->mod_name = "octeon-lmc";
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mci->ctl_name = "octeon-lmc-err";
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mci->edac_check = octeon_lmc_edac_poll;
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if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
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dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
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edac_mc_free(mci);
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return -ENXIO;
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}
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cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
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cfg0.s.intr_ded_ena = 0; /* We poll */
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cfg0.s.intr_sec_ena = 0;
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cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64);
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} else {
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/* OCTEON II */
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union cvmx_lmcx_int_en en;
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union cvmx_lmcx_config config;
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config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));
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if (!config.s.ecc_ena) {
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dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
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return 0;
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}
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mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
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if (!mci)
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return -ENXIO;
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mci->pdev = &pdev->dev;
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mci->dev_name = dev_name(&pdev->dev);
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mci->mod_name = "octeon-lmc";
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mci->ctl_name = "co_lmc_err";
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mci->edac_check = octeon_lmc_edac_poll_o2;
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if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
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dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
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edac_mc_free(mci);
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return -ENXIO;
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}
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en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
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en.s.intr_ded_ena = 0; /* We poll */
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en.s.intr_sec_ena = 0;
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cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);
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}
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platform_set_drvdata(pdev, mci);
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return 0;
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}
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static int octeon_lmc_edac_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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return 0;
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}
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static struct platform_driver octeon_lmc_edac_driver = {
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.probe = octeon_lmc_edac_probe,
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.remove = octeon_lmc_edac_remove,
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.driver = {
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.name = "octeon_lmc_edac",
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}
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};
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module_platform_driver(octeon_lmc_edac_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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