264 lines
6.8 KiB
C
264 lines
6.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
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* Originally split out from the skx_edac driver.
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*
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* Copyright (c) 2018, Intel Corporation.
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*/
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#ifndef _SKX_COMM_EDAC_H
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#define _SKX_COMM_EDAC_H
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#include <linux/bits.h>
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#include <asm/mce.h>
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#define MSG_SIZE 1024
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/*
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* Debug macros
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*/
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#define skx_printk(level, fmt, arg...) \
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edac_printk(level, "skx", fmt, ##arg)
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#define skx_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
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/*
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* Get a bit field at register value <v>, from bit <lo> to bit <hi>
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*/
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#define GET_BITFIELD(v, lo, hi) \
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(((v) & GENMASK_ULL((hi), (lo))) >> (lo))
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#define SKX_NUM_IMC 2 /* Memory controllers per socket */
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#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
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#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
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#define I10NM_NUM_DDR_IMC 12
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#define I10NM_NUM_DDR_CHANNELS 2
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#define I10NM_NUM_DDR_DIMMS 2
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#define I10NM_NUM_HBM_IMC 16
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#define I10NM_NUM_HBM_CHANNELS 2
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#define I10NM_NUM_HBM_DIMMS 1
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#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
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#define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
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#define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
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#define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
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#define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)
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#define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)
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#define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)
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#define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15)
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#define MCI_MISC_ECC_DDRT 8 /* read from DDRT */
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/*
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* According to Intel Architecture spec vol 3B,
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* Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
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* memory errors should fit one of these masks:
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* 000f 0000 1mmm cccc (binary)
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* 000f 0010 1mmm cccc (binary) [RAM used as cache]
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* where:
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* f = Correction Report Filtering Bit. If 1, subsequent errors
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* won't be shown
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* mmm = error type
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* cccc = channel
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*/
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#define MCACOD_MEM_ERR_MASK 0xef80
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/*
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* Errors from either the memory of the 1-level memory system or the
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* 2nd level memory (the slow "far" memory) of the 2-level memory system.
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*/
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#define MCACOD_MEM_CTL_ERR 0x80
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/*
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* Errors from the 1st level memory (the fast "near" memory as cache)
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* of the 2-level memory system.
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*/
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#define MCACOD_EXT_MEM_ERR 0x280
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/*
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* Each cpu socket contains some pci devices that provide global
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* information, and also some that are local to each of the two
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* memory controllers on the die.
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*/
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struct skx_dev {
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struct list_head list;
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u8 bus[4];
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int seg;
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struct pci_dev *sad_all;
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struct pci_dev *util_all;
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struct pci_dev *uracu; /* for i10nm CPU */
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struct pci_dev *pcu_cr3; /* for HBM memory detection */
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u32 mcroute;
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struct skx_imc {
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struct mem_ctl_info *mci;
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struct pci_dev *mdev; /* for i10nm CPU */
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void __iomem *mbase; /* for i10nm CPU */
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int chan_mmio_sz; /* for i10nm CPU */
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int num_channels; /* channels per memory controller */
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int num_dimms; /* dimms per channel */
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bool hbm_mc;
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u8 mc; /* system wide mc# */
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u8 lmc; /* socket relative mc# */
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u8 src_id, node_id;
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struct skx_channel {
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struct pci_dev *cdev;
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struct pci_dev *edev;
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u32 retry_rd_err_log_s;
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u32 retry_rd_err_log_d;
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u32 retry_rd_err_log_d2;
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struct skx_dimm {
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u8 close_pg;
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u8 bank_xor_enable;
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u8 fine_grain_bank;
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u8 rowbits;
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u8 colbits;
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} dimms[NUM_DIMMS];
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} chan[NUM_CHANNELS];
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} imc[NUM_IMC];
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};
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struct skx_pvt {
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struct skx_imc *imc;
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};
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enum type {
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SKX,
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I10NM,
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SPR,
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GNR
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};
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enum {
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INDEX_SOCKET,
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INDEX_MEMCTRL,
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INDEX_CHANNEL,
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INDEX_DIMM,
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INDEX_CS,
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INDEX_NM_FIRST,
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INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
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INDEX_NM_CHANNEL,
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INDEX_NM_DIMM,
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INDEX_NM_CS,
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INDEX_MAX
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};
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#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
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#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
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#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
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#define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
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struct decoded_addr {
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struct mce *mce;
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struct skx_dev *dev;
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u64 addr;
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int socket;
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int imc;
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int channel;
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u64 chan_addr;
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int sktways;
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int chanways;
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int dimm;
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int cs;
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int rank;
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int channel_rank;
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u64 rank_address;
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int row;
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int column;
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int bank_address;
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int bank_group;
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bool decoded_by_adxl;
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};
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struct pci_bdf {
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u32 bus : 8;
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u32 dev : 5;
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u32 fun : 3;
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};
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struct res_config {
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enum type type;
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/* Configuration agent device ID */
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unsigned int decs_did;
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/* Default bus number configuration register offset */
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int busno_cfg_offset;
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/* DDR memory controllers per socket */
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int ddr_imc_num;
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/* DDR channels per DDR memory controller */
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int ddr_chan_num;
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/* DDR DIMMs per DDR memory channel */
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int ddr_dimm_num;
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/* Per DDR channel memory-mapped I/O size */
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int ddr_chan_mmio_sz;
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/* HBM memory controllers per socket */
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int hbm_imc_num;
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/* HBM channels per HBM memory controller */
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int hbm_chan_num;
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/* HBM DIMMs per HBM memory channel */
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int hbm_dimm_num;
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/* Per HBM channel memory-mapped I/O size */
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int hbm_chan_mmio_sz;
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bool support_ddr5;
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/* SAD device BDF */
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struct pci_bdf sad_all_bdf;
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/* PCU device BDF */
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struct pci_bdf pcu_cr3_bdf;
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/* UTIL device BDF */
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struct pci_bdf util_all_bdf;
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/* URACU device BDF */
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struct pci_bdf uracu_bdf;
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/* DDR mdev device BDF */
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struct pci_bdf ddr_mdev_bdf;
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/* HBM mdev device BDF */
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struct pci_bdf hbm_mdev_bdf;
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int sad_all_offset;
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/* Offsets of retry_rd_err_log registers */
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u32 *offsets_scrub;
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u32 *offsets_scrub_hbm0;
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u32 *offsets_scrub_hbm1;
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u32 *offsets_demand;
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u32 *offsets_demand2;
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u32 *offsets_demand_hbm0;
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u32 *offsets_demand_hbm1;
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};
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typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
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struct res_config *cfg);
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typedef bool (*skx_decode_f)(struct decoded_addr *res);
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typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);
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int __init skx_adxl_get(void);
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void __exit skx_adxl_put(void);
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void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
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void skx_set_mem_cfg(bool mem_cfg_2lm);
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int skx_get_src_id(struct skx_dev *d, int off, u8 *id);
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int skx_get_node_id(struct skx_dev *d, u8 *id);
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int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);
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int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);
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int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
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struct skx_imc *imc, int chan, int dimmno,
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struct res_config *cfg);
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int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
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int chan, int dimmno, const char *mod_str);
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int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
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const char *ctl_name, const char *mod_str,
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get_dimm_config_f get_dimm_config,
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struct res_config *cfg);
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int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
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void *data);
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void skx_remove(void);
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#endif /* _SKX_COMM_EDAC_H */
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