304 lines
8.0 KiB
C
304 lines
8.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Atheros AR71XX/AR724X/AR913X GPIO API support
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*
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* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/platform_data/gpio-ath79.h>
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#include <linux/of_device.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#define AR71XX_GPIO_REG_OE 0x00
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#define AR71XX_GPIO_REG_IN 0x04
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#define AR71XX_GPIO_REG_SET 0x0c
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#define AR71XX_GPIO_REG_CLEAR 0x10
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#define AR71XX_GPIO_REG_INT_ENABLE 0x14
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#define AR71XX_GPIO_REG_INT_TYPE 0x18
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#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
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#define AR71XX_GPIO_REG_INT_PENDING 0x20
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#define AR71XX_GPIO_REG_INT_MASK 0x24
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struct ath79_gpio_ctrl {
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struct gpio_chip gc;
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void __iomem *base;
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raw_spinlock_t lock;
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unsigned long both_edges;
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};
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static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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return container_of(gc, struct ath79_gpio_ctrl, gc);
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}
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static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
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{
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return readl(ctrl->base + reg);
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}
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static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
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unsigned reg, u32 val)
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{
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writel(val, ctrl->base + reg);
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}
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static bool ath79_gpio_update_bits(
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struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
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{
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u32 old_val, new_val;
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old_val = ath79_gpio_read(ctrl, reg);
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new_val = (old_val & ~mask) | (bits & mask);
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if (new_val != old_val)
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ath79_gpio_write(ctrl, reg, new_val);
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return new_val != old_val;
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}
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static void ath79_gpio_irq_unmask(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_mask(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_enable(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_disable(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static int ath79_gpio_irq_set_type(struct irq_data *data,
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unsigned int flow_type)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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u32 type = 0, polarity = 0;
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unsigned long flags;
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bool disabled;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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polarity |= mask;
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fallthrough;
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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polarity |= mask;
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fallthrough;
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case IRQ_TYPE_LEVEL_LOW:
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type |= mask;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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if (flow_type == IRQ_TYPE_EDGE_BOTH) {
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ctrl->both_edges |= mask;
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polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
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} else {
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ctrl->both_edges &= ~mask;
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}
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/* As the IRQ configuration can't be loaded atomically we
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* have to disable the interrupt while the configuration state
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* is invalid.
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*/
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disabled = ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
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if (disabled)
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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static struct irq_chip ath79_gpio_irqchip = {
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.name = "gpio-ath79",
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.irq_enable = ath79_gpio_irq_enable,
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.irq_disable = ath79_gpio_irq_disable,
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.irq_mask = ath79_gpio_irq_mask,
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.irq_unmask = ath79_gpio_irq_unmask,
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.irq_set_type = ath79_gpio_irq_set_type,
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};
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static void ath79_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct ath79_gpio_ctrl *ctrl =
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container_of(gc, struct ath79_gpio_ctrl, gc);
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unsigned long flags, pending;
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u32 both_edges, state;
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int irq;
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chained_irq_enter(irqchip, desc);
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
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/* Update the polarity of the both edges irqs */
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both_edges = ctrl->both_edges & pending;
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if (both_edges) {
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state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
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both_edges, ~state);
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}
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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for_each_set_bit(irq, &pending, gc->ngpio)
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generic_handle_domain_irq(gc->irq.domain, irq);
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chained_irq_exit(irqchip, desc);
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}
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static const struct of_device_id ath79_gpio_of_match[] = {
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{ .compatible = "qca,ar7100-gpio" },
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{ .compatible = "qca,ar9340-gpio" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
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static int ath79_gpio_probe(struct platform_device *pdev)
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{
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struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct ath79_gpio_ctrl *ctrl;
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struct gpio_irq_chip *girq;
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u32 ath79_gpio_count;
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bool oe_inverted;
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int err;
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ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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if (np) {
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err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
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if (err) {
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dev_err(dev, "ngpios property is not valid\n");
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return err;
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}
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oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
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} else if (pdata) {
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ath79_gpio_count = pdata->ngpios;
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oe_inverted = pdata->oe_inverted;
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} else {
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dev_err(dev, "No DT node or platform data found\n");
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return -EINVAL;
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}
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if (ath79_gpio_count >= 32) {
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dev_err(dev, "ngpios must be less than 32\n");
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return -EINVAL;
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}
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ctrl->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ctrl->base))
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return PTR_ERR(ctrl->base);
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raw_spin_lock_init(&ctrl->lock);
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err = bgpio_init(&ctrl->gc, dev, 4,
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ctrl->base + AR71XX_GPIO_REG_IN,
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ctrl->base + AR71XX_GPIO_REG_SET,
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ctrl->base + AR71XX_GPIO_REG_CLEAR,
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oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
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oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
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0);
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if (err) {
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dev_err(dev, "bgpio_init failed\n");
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return err;
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}
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/* Use base 0 to stay compatible with legacy platforms */
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ctrl->gc.base = 0;
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/* Optional interrupt setup */
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if (!np || of_property_read_bool(np, "interrupt-controller")) {
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girq = &ctrl->gc.irq;
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girq->chip = &ath79_gpio_irqchip;
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girq->parent_handler = ath79_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = platform_get_irq(pdev, 0);
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_simple_irq;
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}
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return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
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}
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static struct platform_driver ath79_gpio_driver = {
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.driver = {
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.name = "ath79-gpio",
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.of_match_table = ath79_gpio_of_match,
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},
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.probe = ath79_gpio_probe,
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};
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module_platform_driver(ath79_gpio_driver);
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MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
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MODULE_LICENSE("GPL v2");
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