59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_IMU_H__
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#define __AMDGPU_IMU_H__
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enum imu_work_mode {
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DEBUG_MODE,
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MISSION_MODE
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};
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struct amdgpu_imu_funcs {
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int (*init_microcode)(struct amdgpu_device *adev);
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int (*load_microcode)(struct amdgpu_device *adev);
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void (*setup_imu)(struct amdgpu_device *adev);
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int (*start_imu)(struct amdgpu_device *adev);
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void (*program_rlc_ram)(struct amdgpu_device *adev);
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int (*wait_for_reset_status)(struct amdgpu_device *adev);
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};
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struct imu_rlc_ram_golden {
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u32 hwip;
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u32 instance;
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u32 segment;
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u32 reg;
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u32 data;
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u32 addr_mask;
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};
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#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
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{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
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struct amdgpu_imu {
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const struct amdgpu_imu_funcs *funcs;
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enum imu_work_mode mode;
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};
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#endif
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