309 lines
8.2 KiB
C
309 lines
8.2 KiB
C
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu_vm.h"
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#include "amdgpu_job.h"
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#include "amdgpu_object.h"
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#include "amdgpu_trace.h"
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#define AMDGPU_VM_SDMA_MIN_NUM_DW 256u
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#define AMDGPU_VM_SDMA_MAX_NUM_DW (16u * 1024u)
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/**
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* amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped
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*
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* @table: newly allocated or validated PD/PT
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*/
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static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)
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{
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int r;
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r = amdgpu_ttm_alloc_gart(&table->bo.tbo);
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if (r)
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return r;
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if (table->shadow)
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r = amdgpu_ttm_alloc_gart(&table->shadow->tbo);
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return r;
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}
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/* Allocate a new job for @count PTE updates */
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static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
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unsigned int count)
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{
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enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
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: AMDGPU_IB_POOL_DELAYED;
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struct drm_sched_entity *entity = p->immediate ? &p->vm->immediate
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: &p->vm->delayed;
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unsigned int ndw;
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int r;
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/* estimate how many dw we need */
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ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
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if (p->pages_addr)
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ndw += count * 2;
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ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
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r = amdgpu_job_alloc_with_ib(p->adev, entity, AMDGPU_FENCE_OWNER_VM,
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ndw * 4, pool, &p->job);
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if (r)
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return r;
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p->num_dw_left = ndw;
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return 0;
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}
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/**
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* amdgpu_vm_sdma_prepare - prepare SDMA command submission
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*
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* @p: see amdgpu_vm_update_params definition
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* @resv: reservation object with embedded fence
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* @sync_mode: synchronization mode
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*
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* Returns:
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* Negativ errno, 0 for success.
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*/
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static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
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struct dma_resv *resv,
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enum amdgpu_sync_mode sync_mode)
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{
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struct amdgpu_sync sync;
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int r;
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r = amdgpu_vm_sdma_alloc_job(p, 0);
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if (r)
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return r;
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if (!resv)
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return 0;
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amdgpu_sync_create(&sync);
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r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, p->vm);
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if (!r)
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r = amdgpu_sync_push_to_job(&sync, p->job);
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amdgpu_sync_free(&sync);
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return r;
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}
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/**
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* amdgpu_vm_sdma_commit - commit SDMA command submission
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*
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* @p: see amdgpu_vm_update_params definition
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* @fence: resulting fence
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*
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* Returns:
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* Negativ errno, 0 for success.
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*/
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static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
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struct dma_fence **fence)
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{
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struct amdgpu_ib *ib = p->job->ibs;
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struct amdgpu_ring *ring;
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struct dma_fence *f;
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ring = container_of(p->vm->delayed.rq->sched, struct amdgpu_ring,
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sched);
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WARN_ON(ib->length_dw == 0);
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amdgpu_ring_pad_ib(ring, ib);
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WARN_ON(ib->length_dw > p->num_dw_left);
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f = amdgpu_job_submit(p->job);
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if (p->unlocked) {
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struct dma_fence *tmp = dma_fence_get(f);
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swap(p->vm->last_unlocked, tmp);
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dma_fence_put(tmp);
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} else {
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dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f,
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DMA_RESV_USAGE_BOOKKEEP);
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}
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if (fence && !p->immediate) {
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/*
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* Most hw generations now have a separate queue for page table
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* updates, but when the queue is shared with userspace we need
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* the extra CPU round trip to correctly flush the TLB.
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*/
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set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
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swap(*fence, f);
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}
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dma_fence_put(f);
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return 0;
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}
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/**
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* amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
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*
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* @p: see amdgpu_vm_update_params definition
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* @bo: PD/PT to update
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* @pe: addr of the page entry
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* @count: number of page entries to copy
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*
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* Traces the parameters and calls the DMA function to copy the PTEs.
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*/
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static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
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struct amdgpu_bo *bo, uint64_t pe,
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unsigned count)
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{
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struct amdgpu_ib *ib = p->job->ibs;
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uint64_t src = ib->gpu_addr;
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src += p->num_dw_left * 4;
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pe += amdgpu_gmc_sign_extend(amdgpu_bo_gpu_offset_no_check(bo));
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trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate);
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amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
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}
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/**
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* amdgpu_vm_sdma_set_ptes - helper to call the right asic function
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*
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* @p: see amdgpu_vm_update_params definition
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* @bo: PD/PT to update
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* @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Traces the parameters and calls the right asic functions
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* to setup the page table using the DMA.
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*/
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static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
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struct amdgpu_bo *bo, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint64_t flags)
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{
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struct amdgpu_ib *ib = p->job->ibs;
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pe += amdgpu_gmc_sign_extend(amdgpu_bo_gpu_offset_no_check(bo));
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trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
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if (count < 3) {
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amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
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count, incr);
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} else {
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amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr,
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count, incr, flags);
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}
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}
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/**
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* amdgpu_vm_sdma_update - execute VM update
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*
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* @p: see amdgpu_vm_update_params definition
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* @vmbo: PD/PT to update
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* @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Reserve space in the IB, setup mapping buffer on demand and write commands to
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* the IB.
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*/
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static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
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struct amdgpu_bo_vm *vmbo, uint64_t pe,
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uint64_t addr, unsigned count, uint32_t incr,
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uint64_t flags)
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{
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struct amdgpu_bo *bo = &vmbo->bo;
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struct dma_resv_iter cursor;
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unsigned int i, ndw, nptes;
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struct dma_fence *fence;
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uint64_t *pte;
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int r;
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/* Wait for PD/PT moves to be completed */
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dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL);
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dma_resv_for_each_fence_unlocked(&cursor, fence) {
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dma_fence_get(fence);
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r = drm_sched_job_add_dependency(&p->job->base, fence);
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if (r) {
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dma_fence_put(fence);
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dma_resv_iter_end(&cursor);
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return r;
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}
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}
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dma_resv_iter_end(&cursor);
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do {
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ndw = p->num_dw_left;
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ndw -= p->job->ibs->length_dw;
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if (ndw < 32) {
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r = amdgpu_vm_sdma_commit(p, NULL);
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if (r)
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return r;
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r = amdgpu_vm_sdma_alloc_job(p, count);
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if (r)
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return r;
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}
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if (!p->pages_addr) {
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/* set page commands needed */
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if (vmbo->shadow)
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amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr,
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count, incr, flags);
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amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
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incr, flags);
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return 0;
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}
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/* copy commands needed */
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ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
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(vmbo->shadow ? 2 : 1);
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/* for padding */
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ndw -= 7;
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nptes = min(count, ndw / 2);
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/* Put the PTEs at the end of the IB. */
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p->num_dw_left -= nptes * 2;
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pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]);
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for (i = 0; i < nptes; ++i, addr += incr) {
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pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr);
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pte[i] |= flags;
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}
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if (vmbo->shadow)
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amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes);
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amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
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pe += nptes * 8;
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count -= nptes;
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} while (count);
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return 0;
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}
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const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = {
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.map_table = amdgpu_vm_sdma_map_table,
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.prepare = amdgpu_vm_sdma_prepare,
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.update = amdgpu_vm_sdma_update,
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.commit = amdgpu_vm_sdma_commit
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};
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