249 lines
7.9 KiB
C
249 lines
7.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2014-2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "kfd_mqd_manager.h"
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#include "amdgpu_amdkfd.h"
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#include "kfd_device_queue_manager.h"
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/* Mapping queue priority to pipe priority, indexed by queue priority */
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int pipe_priority_map[] = {
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH
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};
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struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_dev *dev, struct queue_properties *q)
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{
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struct kfd_mem_obj *mqd_mem_obj = NULL;
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mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
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if (!mqd_mem_obj)
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return NULL;
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mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem;
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mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
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mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr;
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return mqd_mem_obj;
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}
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struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_dev *dev,
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struct queue_properties *q)
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{
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struct kfd_mem_obj *mqd_mem_obj = NULL;
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uint64_t offset;
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mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
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if (!mqd_mem_obj)
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return NULL;
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offset = (q->sdma_engine_id *
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dev->device_info.num_sdma_queues_per_engine +
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q->sdma_queue_id) *
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dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size;
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offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
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mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem
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+ offset);
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mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
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mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
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dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);
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return mqd_mem_obj;
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}
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void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
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struct kfd_mem_obj *mqd_mem_obj)
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{
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WARN_ON(!mqd_mem_obj->gtt_mem);
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kfree(mqd_mem_obj);
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}
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void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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const uint32_t *cu_mask, uint32_t cu_mask_count,
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uint32_t *se_mask)
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{
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struct kfd_cu_info cu_info;
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uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
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bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);
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uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;
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int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1;
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amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
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if (cu_mask_count > cu_info.cu_active_number)
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cu_mask_count = cu_info.cu_active_number;
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/* Exceeding these bounds corrupts the stack and indicates a coding error.
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* Returning with no CU's enabled will hang the queue, which should be
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* attention grabbing.
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*/
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if (cu_info.num_shader_engines > KFD_MAX_NUM_SE) {
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pr_err("Exceeded KFD_MAX_NUM_SE, chip reports %d\n", cu_info.num_shader_engines);
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return;
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}
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if (cu_info.num_shader_arrays_per_engine > KFD_MAX_NUM_SH_PER_SE) {
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pr_err("Exceeded KFD_MAX_NUM_SH, chip reports %d\n",
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cu_info.num_shader_arrays_per_engine * cu_info.num_shader_engines);
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return;
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}
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cu_bitmap_sh_mul = (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0) &&
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KFD_GC_VERSION(mm->dev) < IP_VERSION(12, 0, 0)) ? 2 : 1;
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/* Count active CUs per SH.
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*
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* Some CUs in an SH may be disabled. HW expects disabled CUs to be
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* represented in the high bits of each SH's enable mask (the upper and lower
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* 16 bits of se_mask) and will take care of the actual distribution of
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* disabled CUs within each SH automatically.
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* Each half of se_mask must be filled only on bits 0-cu_per_sh[se][sh]-1.
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*
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* See note on Arcturus cu_bitmap layout in gfx_v9_0_get_cu_info.
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* See note on GFX11 cu_bitmap layout in gfx_v11_0_get_cu_info.
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*/
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for (se = 0; se < cu_info.num_shader_engines; se++)
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for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
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cu_per_sh[se][sh] = hweight32(
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cu_info.cu_bitmap[se % 4][sh + (se / 4) * cu_bitmap_sh_mul]);
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/* Symmetrically map cu_mask to all SEs & SHs:
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* se_mask programs up to 2 SH in the upper and lower 16 bits.
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*
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* Examples
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* Assuming 1 SH/SE, 4 SEs:
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* cu_mask[0] bit0 -> se_mask[0] bit0
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* cu_mask[0] bit1 -> se_mask[1] bit0
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* ...
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* cu_mask[0] bit4 -> se_mask[0] bit1
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* ...
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*
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* Assuming 2 SH/SE, 4 SEs
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* cu_mask[0] bit0 -> se_mask[0] bit0 (SE0,SH0,CU0)
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* cu_mask[0] bit1 -> se_mask[1] bit0 (SE1,SH0,CU0)
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* ...
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* cu_mask[0] bit4 -> se_mask[0] bit16 (SE0,SH1,CU0)
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* cu_mask[0] bit5 -> se_mask[1] bit16 (SE1,SH1,CU0)
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* ...
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* cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1)
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* ...
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*
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* First ensure all CUs are disabled, then enable user specified CUs.
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*/
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for (i = 0; i < cu_info.num_shader_engines; i++)
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se_mask[i] = 0;
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i = 0;
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for (cu = 0; cu < 16; cu += inc) {
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for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
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for (se = 0; se < cu_info.num_shader_engines; se++) {
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if (cu_per_sh[se][sh] > cu) {
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if (cu_mask[i / 32] & (en_mask << (i % 32)))
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se_mask[se] |= en_mask << (cu + sh * 16);
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i += inc;
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if (i == cu_mask_count)
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return;
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}
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}
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}
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}
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}
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int kfd_hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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struct queue_properties *p, struct mm_struct *mms)
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{
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return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id,
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queue_id, p->doorbell_off);
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}
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int kfd_destroy_mqd_cp(struct mqd_manager *mm, void *mqd,
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enum kfd_preempt_type type, unsigned int timeout,
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uint32_t pipe_id, uint32_t queue_id)
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{
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return mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, mqd, type, timeout,
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pipe_id, queue_id);
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}
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void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd,
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struct kfd_mem_obj *mqd_mem_obj)
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{
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if (mqd_mem_obj->gtt_mem) {
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amdgpu_amdkfd_free_gtt_mem(mm->dev->adev, mqd_mem_obj->gtt_mem);
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kfree(mqd_mem_obj);
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} else {
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kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
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}
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}
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bool kfd_is_occupied_cp(struct mqd_manager *mm, void *mqd,
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uint64_t queue_address, uint32_t pipe_id,
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uint32_t queue_id)
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{
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return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->adev, queue_address,
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pipe_id, queue_id);
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}
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int kfd_load_mqd_sdma(struct mqd_manager *mm, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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struct queue_properties *p, struct mm_struct *mms)
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{
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return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd,
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(uint32_t __user *)p->write_ptr,
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mms);
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}
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/*
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* preempt type here is ignored because there is only one way
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* to preempt sdma queue
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*/
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int kfd_destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
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enum kfd_preempt_type type,
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unsigned int timeout, uint32_t pipe_id,
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uint32_t queue_id)
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{
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return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout);
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}
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bool kfd_is_occupied_sdma(struct mqd_manager *mm, void *mqd,
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uint64_t queue_address, uint32_t pipe_id,
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uint32_t queue_id)
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{
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return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd);
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}
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