314 lines
11 KiB
C
314 lines
11 KiB
C
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/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _DCE_ABM_H_
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#define _DCE_ABM_H_
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#include "abm.h"
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#define ABM_COMMON_REG_LIST_DCE_BASE() \
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SR(MASTER_COMM_CNTL_REG), \
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SR(MASTER_COMM_CMD_REG), \
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SR(MASTER_COMM_DATA_REG1)
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#define ABM_DCE110_COMMON_REG_LIST() \
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SR(DC_ABM1_HG_SAMPLE_RATE), \
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SR(DC_ABM1_LS_SAMPLE_RATE), \
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SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
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SR(DC_ABM1_HG_MISC_CTRL), \
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SR(DC_ABM1_IPCSC_COEFF_SEL), \
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SR(BL1_PWM_CURRENT_ABM_LEVEL), \
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SR(BL1_PWM_TARGET_ABM_LEVEL), \
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SR(BL1_PWM_USER_LEVEL), \
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SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
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SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
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SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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SR(DC_ABM1_ACE_THRES_12), \
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SR(BIOS_SCRATCH_2)
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#define ABM_DCN10_REG_LIST(id)\
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
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SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
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SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN20_REG_LIST() \
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SR(DC_ABM1_HG_SAMPLE_RATE), \
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SR(DC_ABM1_LS_SAMPLE_RATE), \
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SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
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SR(DC_ABM1_HG_MISC_CTRL), \
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SR(DC_ABM1_IPCSC_COEFF_SEL), \
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SR(BL1_PWM_CURRENT_ABM_LEVEL), \
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SR(BL1_PWM_TARGET_ABM_LEVEL), \
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SR(BL1_PWM_USER_LEVEL), \
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SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
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SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
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SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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SR(DC_ABM1_ACE_THRES_12), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN301_REG_LIST(id)\
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
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SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
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SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN302_REG_LIST(id)\
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
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SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
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SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN30_REG_LIST(id)\
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
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SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
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SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN32_REG_LIST(id)\
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
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SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
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SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
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ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
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ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
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ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
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#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
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ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
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ABM_SF(DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
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ABM_SF(DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_VMAX_SEL, mask_sh), \
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ABM_SF(DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
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ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
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ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
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ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
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ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
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BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
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ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
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BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
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ABM_SF(BL1_PWM_USER_LEVEL, \
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BL1_PWM_USER_LEVEL, mask_sh), \
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ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
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ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
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ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
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ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
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ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
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ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
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ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
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#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
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ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_VMAX_SEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
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ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
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BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
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ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
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BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
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ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
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BL1_PWM_USER_LEVEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
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ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
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ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
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#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
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#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
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#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
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ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_VMAX_SEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
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ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
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ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
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ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
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BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
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ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
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BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
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ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
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BL1_PWM_USER_LEVEL, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
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ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
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ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
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ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
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ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
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#define ABM_REG_FIELD_LIST(type) \
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type ABM1_HG_NUM_OF_BINS_SEL; \
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type ABM1_HG_VMAX_SEL; \
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type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
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type ABM1_IPCSC_COEFF_SEL_R; \
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type ABM1_IPCSC_COEFF_SEL_G; \
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type ABM1_IPCSC_COEFF_SEL_B; \
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type BL1_PWM_CURRENT_ABM_LEVEL; \
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type BL1_PWM_TARGET_ABM_LEVEL; \
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type BL1_PWM_USER_LEVEL; \
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type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
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type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
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type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
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type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
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type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
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type MASTER_COMM_INTERRUPT; \
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type MASTER_COMM_CMD_REG_BYTE0; \
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type MASTER_COMM_CMD_REG_BYTE1; \
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type MASTER_COMM_CMD_REG_BYTE2
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struct dce_abm_shift {
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ABM_REG_FIELD_LIST(uint8_t);
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};
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struct dce_abm_mask {
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ABM_REG_FIELD_LIST(uint32_t);
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};
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struct dce_abm_registers {
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uint32_t DC_ABM1_HG_SAMPLE_RATE;
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uint32_t DC_ABM1_LS_SAMPLE_RATE;
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||
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uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
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||
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uint32_t DC_ABM1_HG_MISC_CTRL;
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||
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uint32_t DC_ABM1_IPCSC_COEFF_SEL;
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||
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uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
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||
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uint32_t BL1_PWM_TARGET_ABM_LEVEL;
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||
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uint32_t BL1_PWM_USER_LEVEL;
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||
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uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
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||
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uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
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||
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uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
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||
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uint32_t DC_ABM1_ACE_THRES_12;
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||
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uint32_t MASTER_COMM_CNTL_REG;
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||
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uint32_t MASTER_COMM_CMD_REG;
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||
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uint32_t MASTER_COMM_DATA_REG1;
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||
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uint32_t BIOS_SCRATCH_2;
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||
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};
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||
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||
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struct dce_abm {
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||
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struct abm base;
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||
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const struct dce_abm_registers *regs;
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||
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const struct dce_abm_shift *abm_shift;
|
||
|
|
const struct dce_abm_mask *abm_mask;
|
||
|
|
};
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||
|
|
|
||
|
|
struct abm *dce_abm_create(
|
||
|
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struct dc_context *ctx,
|
||
|
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const struct dce_abm_registers *regs,
|
||
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const struct dce_abm_shift *abm_shift,
|
||
|
|
const struct dce_abm_mask *abm_mask);
|
||
|
|
|
||
|
|
void dce_abm_destroy(struct abm **abm);
|
||
|
|
|
||
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#endif /* _DCE_ABM_H_ */
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