312 lines
8.8 KiB
C
312 lines
8.8 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dce_ipp.h"
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#include "reg_helper.h"
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#include "dm_services.h"
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#define REG(reg) \
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(ipp_dce->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
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#define CTX \
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ipp_dce->base.ctx
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static void dce_ipp_cursor_set_position(
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struct input_pixel_processor *ipp,
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const struct dc_cursor_position *position,
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const struct dc_cursor_mi_param *param)
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{
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struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
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/* lock cursor registers */
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REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
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/* Flag passed in structure differentiates cursor enable/disable. */
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/* Update if it differs from cached state. */
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REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
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REG_SET_2(CUR_POSITION, 0,
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CURSOR_X_POSITION, position->x,
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CURSOR_Y_POSITION, position->y);
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REG_SET_2(CUR_HOT_SPOT, 0,
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CURSOR_HOT_SPOT_X, position->x_hotspot,
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CURSOR_HOT_SPOT_Y, position->y_hotspot);
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/* unlock cursor registers */
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REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
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}
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static void dce_ipp_cursor_set_attributes(
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struct input_pixel_processor *ipp,
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const struct dc_cursor_attributes *attributes)
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{
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struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
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int mode;
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/* Lock cursor registers */
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REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
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/* Program cursor control */
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switch (attributes->color_format) {
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case CURSOR_MODE_MONO:
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mode = 0;
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break;
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case CURSOR_MODE_COLOR_1BIT_AND:
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mode = 1;
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break;
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case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
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mode = 2;
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break;
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case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
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mode = 3;
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break;
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default:
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BREAK_TO_DEBUGGER(); /* unsupported */
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mode = 0;
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}
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REG_UPDATE_3(CUR_CONTROL,
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CURSOR_MODE, mode,
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CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
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CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
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if (attributes->color_format == CURSOR_MODE_MONO) {
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REG_SET_3(CUR_COLOR1, 0,
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CUR_COLOR1_BLUE, 0,
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CUR_COLOR1_GREEN, 0,
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CUR_COLOR1_RED, 0);
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REG_SET_3(CUR_COLOR2, 0,
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CUR_COLOR2_BLUE, 0xff,
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CUR_COLOR2_GREEN, 0xff,
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CUR_COLOR2_RED, 0xff);
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}
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/*
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* Program cursor size -- NOTE: HW spec specifies that HW register
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* stores size as (height - 1, width - 1)
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*/
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REG_SET_2(CUR_SIZE, 0,
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CURSOR_WIDTH, attributes->width-1,
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CURSOR_HEIGHT, attributes->height-1);
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/* Program cursor surface address */
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/* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor
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* surface base address in byte. It is 4K byte aligned.
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* The correct way to program cursor surface address is to first write
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* to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS
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*/
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REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,
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CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part);
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REG_SET(CUR_SURFACE_ADDRESS, 0,
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CURSOR_SURFACE_ADDRESS, attributes->address.low_part);
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/* Unlock Cursor registers. */
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REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
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}
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static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
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struct ipp_prescale_params *params)
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{
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struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
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/* set to bypass mode first before change */
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REG_UPDATE(PRESCALE_GRPH_CONTROL,
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GRPH_PRESCALE_BYPASS, 1);
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REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
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GRPH_PRESCALE_SCALE_R, params->scale,
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GRPH_PRESCALE_BIAS_R, params->bias);
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REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
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GRPH_PRESCALE_SCALE_G, params->scale,
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GRPH_PRESCALE_BIAS_G, params->bias);
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REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
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GRPH_PRESCALE_SCALE_B, params->scale,
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GRPH_PRESCALE_BIAS_B, params->bias);
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if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
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REG_UPDATE(PRESCALE_GRPH_CONTROL,
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GRPH_PRESCALE_BYPASS, 0);
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/* If prescale is in use, then legacy lut should be bypassed */
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REG_UPDATE(INPUT_GAMMA_CONTROL,
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GRPH_INPUT_GAMMA_MODE, 1);
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}
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}
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static void dce_ipp_program_input_lut(
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struct input_pixel_processor *ipp,
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const struct dc_gamma *gamma)
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{
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int i;
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struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
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/* power on LUT memory */
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if (REG(DCFE_MEM_PWR_CTRL))
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REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
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/* enable all */
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REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
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/* 256 entry mode */
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REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
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/* LUT-256, unsigned, integer, new u0.12 format */
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REG_SET_3(DC_LUT_CONTROL, 0,
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DC_LUT_DATA_R_FORMAT, 3,
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DC_LUT_DATA_G_FORMAT, 3,
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DC_LUT_DATA_B_FORMAT, 3);
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/* start from index 0 */
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REG_SET(DC_LUT_RW_INDEX, 0,
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DC_LUT_RW_INDEX, 0);
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for (i = 0; i < gamma->num_entries; i++) {
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REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
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dc_fixpt_round(
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gamma->entries.red[i]));
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REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
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dc_fixpt_round(
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gamma->entries.green[i]));
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REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
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dc_fixpt_round(
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gamma->entries.blue[i]));
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}
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/* power off LUT memory */
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if (REG(DCFE_MEM_PWR_CTRL))
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REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
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/* bypass prescale, enable legacy LUT */
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REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
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REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
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}
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static void dce_ipp_set_degamma(
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struct input_pixel_processor *ipp,
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enum ipp_degamma_mode mode)
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{
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struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
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uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
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ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
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REG_SET_3(DEGAMMA_CONTROL, 0,
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GRPH_DEGAMMA_MODE, degamma_type,
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CURSOR_DEGAMMA_MODE, degamma_type,
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CURSOR2_DEGAMMA_MODE, degamma_type);
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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static void dce60_ipp_set_degamma(
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struct input_pixel_processor *ipp,
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enum ipp_degamma_mode mode)
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{
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struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
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uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
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ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
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/* DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL reg */
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REG_SET_2(DEGAMMA_CONTROL, 0,
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GRPH_DEGAMMA_MODE, degamma_type,
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CURSOR_DEGAMMA_MODE, degamma_type);
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}
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#endif
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static const struct ipp_funcs dce_ipp_funcs = {
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.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
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.ipp_cursor_set_position = dce_ipp_cursor_set_position,
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.ipp_program_prescale = dce_ipp_program_prescale,
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.ipp_program_input_lut = dce_ipp_program_input_lut,
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.ipp_set_degamma = dce_ipp_set_degamma
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};
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#if defined(CONFIG_DRM_AMD_DC_SI)
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static const struct ipp_funcs dce60_ipp_funcs = {
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.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
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.ipp_cursor_set_position = dce_ipp_cursor_set_position,
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.ipp_program_prescale = dce_ipp_program_prescale,
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.ipp_program_input_lut = dce_ipp_program_input_lut,
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.ipp_set_degamma = dce60_ipp_set_degamma
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};
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#endif
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/*****************************************/
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/* Constructor, Destructor */
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/*****************************************/
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void dce_ipp_construct(
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struct dce_ipp *ipp_dce,
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struct dc_context *ctx,
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int inst,
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const struct dce_ipp_registers *regs,
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const struct dce_ipp_shift *ipp_shift,
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const struct dce_ipp_mask *ipp_mask)
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{
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ipp_dce->base.ctx = ctx;
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ipp_dce->base.inst = inst;
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ipp_dce->base.funcs = &dce_ipp_funcs;
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ipp_dce->regs = regs;
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ipp_dce->ipp_shift = ipp_shift;
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ipp_dce->ipp_mask = ipp_mask;
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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void dce60_ipp_construct(
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struct dce_ipp *ipp_dce,
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struct dc_context *ctx,
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int inst,
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const struct dce_ipp_registers *regs,
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const struct dce_ipp_shift *ipp_shift,
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const struct dce_ipp_mask *ipp_mask)
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{
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ipp_dce->base.ctx = ctx;
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ipp_dce->base.inst = inst;
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ipp_dce->base.funcs = &dce60_ipp_funcs;
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ipp_dce->regs = regs;
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ipp_dce->ipp_shift = ipp_shift;
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ipp_dce->ipp_mask = ipp_mask;
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}
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#endif
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void dce_ipp_destroy(struct input_pixel_processor **ipp)
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{
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kfree(TO_DCE_IPP(*ipp));
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*ipp = NULL;
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}
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