288 lines
11 KiB
C
288 lines
11 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _DCE_IPP_H_
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#define _DCE_IPP_H_
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#include "ipp.h"
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#define TO_DCE_IPP(ipp)\
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container_of(ipp, struct dce_ipp, base)
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#define IPP_COMMON_REG_LIST_DCE_BASE(id) \
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SRI(CUR_UPDATE, DCP, id), \
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SRI(CUR_CONTROL, DCP, id), \
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SRI(CUR_POSITION, DCP, id), \
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SRI(CUR_HOT_SPOT, DCP, id), \
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SRI(CUR_COLOR1, DCP, id), \
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SRI(CUR_COLOR2, DCP, id), \
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SRI(CUR_SIZE, DCP, id), \
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SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
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SRI(CUR_SURFACE_ADDRESS, DCP, id), \
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SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
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SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
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SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
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SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
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SRI(INPUT_GAMMA_CONTROL, DCP, id), \
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SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
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SRI(DC_LUT_RW_MODE, DCP, id), \
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SRI(DC_LUT_CONTROL, DCP, id), \
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SRI(DC_LUT_RW_INDEX, DCP, id), \
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SRI(DC_LUT_SEQ_COLOR, DCP, id), \
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SRI(DEGAMMA_CONTROL, DCP, id)
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#define IPP_DCE100_REG_LIST_DCE_BASE(id) \
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IPP_COMMON_REG_LIST_DCE_BASE(id), \
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SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
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#define IPP_DCE110_REG_LIST_DCE_BASE(id) \
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IPP_COMMON_REG_LIST_DCE_BASE(id), \
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SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
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#define IPP_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
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IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
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IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
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IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
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IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
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IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
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IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
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IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
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IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
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IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
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IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
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IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
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IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
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IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
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IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
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IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
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IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
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IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
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IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
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IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
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IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
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IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
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IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
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IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
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IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
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IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
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IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
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IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
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IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
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IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
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#define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
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IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
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#define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \
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IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
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IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
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IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
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IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
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IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
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IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
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IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
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IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
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IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
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IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
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IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
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IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
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IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
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IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
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IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \
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IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
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IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
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IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
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IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
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IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
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IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
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IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
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IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
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IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
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IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
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IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
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IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
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IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
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IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
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IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
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IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
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IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
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IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
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IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
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IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
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IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
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IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
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#if defined(CONFIG_DRM_AMD_DC_SI)
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#define IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
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IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
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IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
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IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
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IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
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IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
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IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
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IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
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IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
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IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
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IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
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IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
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IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
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IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
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IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
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IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
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IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
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IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
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IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
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IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
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IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
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IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
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IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
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IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
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IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
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IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
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IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
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IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
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IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
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IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh)
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#endif
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#define IPP_REG_FIELD_LIST(type) \
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type CURSOR_UPDATE_LOCK; \
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type CURSOR_EN; \
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type CURSOR_X_POSITION; \
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type CURSOR_Y_POSITION; \
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type CURSOR_HOT_SPOT_X; \
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type CURSOR_HOT_SPOT_Y; \
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type CURSOR_MODE; \
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type CURSOR_2X_MAGNIFY; \
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type CUR_INV_TRANS_CLAMP; \
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type CUR_COLOR1_BLUE; \
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type CUR_COLOR1_GREEN; \
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type CUR_COLOR1_RED; \
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type CUR_COLOR2_BLUE; \
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type CUR_COLOR2_GREEN; \
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type CUR_COLOR2_RED; \
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type CURSOR_WIDTH; \
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type CURSOR_HEIGHT; \
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type CURSOR_SURFACE_ADDRESS_HIGH; \
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type CURSOR_SURFACE_ADDRESS; \
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type GRPH_PRESCALE_BYPASS; \
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type GRPH_PRESCALE_SCALE_R; \
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type GRPH_PRESCALE_BIAS_R; \
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type GRPH_PRESCALE_SCALE_G; \
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type GRPH_PRESCALE_BIAS_G; \
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type GRPH_PRESCALE_SCALE_B; \
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type GRPH_PRESCALE_BIAS_B; \
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type GRPH_INPUT_GAMMA_MODE; \
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type DCP_LUT_MEM_PWR_DIS; \
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type DC_LUT_WRITE_EN_MASK; \
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type DC_LUT_RW_MODE; \
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type DC_LUT_DATA_R_FORMAT; \
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type DC_LUT_DATA_G_FORMAT; \
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type DC_LUT_DATA_B_FORMAT; \
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type DC_LUT_RW_INDEX; \
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type DC_LUT_SEQ_COLOR; \
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type GRPH_DEGAMMA_MODE; \
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type CURSOR_DEGAMMA_MODE; \
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type CURSOR2_DEGAMMA_MODE
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struct dce_ipp_shift {
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IPP_REG_FIELD_LIST(uint8_t);
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};
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struct dce_ipp_mask {
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IPP_REG_FIELD_LIST(uint32_t);
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};
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struct dce_ipp_registers {
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uint32_t CUR_UPDATE;
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uint32_t CUR_CONTROL;
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uint32_t CUR_POSITION;
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uint32_t CUR_HOT_SPOT;
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uint32_t CUR_COLOR1;
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uint32_t CUR_COLOR2;
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uint32_t CUR_SIZE;
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uint32_t CUR_SURFACE_ADDRESS_HIGH;
|
||
|
|
uint32_t CUR_SURFACE_ADDRESS;
|
||
|
|
uint32_t PRESCALE_GRPH_CONTROL;
|
||
|
|
uint32_t PRESCALE_VALUES_GRPH_R;
|
||
|
|
uint32_t PRESCALE_VALUES_GRPH_G;
|
||
|
|
uint32_t PRESCALE_VALUES_GRPH_B;
|
||
|
|
uint32_t INPUT_GAMMA_CONTROL;
|
||
|
|
uint32_t DCFE_MEM_PWR_CTRL;
|
||
|
|
uint32_t DC_LUT_WRITE_EN_MASK;
|
||
|
|
uint32_t DC_LUT_RW_MODE;
|
||
|
|
uint32_t DC_LUT_CONTROL;
|
||
|
|
uint32_t DC_LUT_RW_INDEX;
|
||
|
|
uint32_t DC_LUT_SEQ_COLOR;
|
||
|
|
uint32_t DEGAMMA_CONTROL;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dce_ipp {
|
||
|
|
struct input_pixel_processor base;
|
||
|
|
const struct dce_ipp_registers *regs;
|
||
|
|
const struct dce_ipp_shift *ipp_shift;
|
||
|
|
const struct dce_ipp_mask *ipp_mask;
|
||
|
|
};
|
||
|
|
|
||
|
|
void dce_ipp_construct(struct dce_ipp *ipp_dce,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
int inst,
|
||
|
|
const struct dce_ipp_registers *regs,
|
||
|
|
const struct dce_ipp_shift *ipp_shift,
|
||
|
|
const struct dce_ipp_mask *ipp_mask);
|
||
|
|
|
||
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
||
|
|
void dce60_ipp_construct(struct dce_ipp *ipp_dce,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
int inst,
|
||
|
|
const struct dce_ipp_registers *regs,
|
||
|
|
const struct dce_ipp_shift *ipp_shift,
|
||
|
|
const struct dce_ipp_mask *ipp_mask);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void dce_ipp_destroy(struct input_pixel_processor **ipp);
|
||
|
|
|
||
|
|
#endif /* _DCE_IPP_H_ */
|