135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
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/*
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* Copyright 2012-17 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#include "reg_helper.h"
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#include "resource.h"
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#include "dwb.h"
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#include "dcn10_dwb.h"
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#define REG(reg)\
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dwbc10->dwbc_regs->reg
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#define CTX \
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dwbc10->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
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#define TO_DCN10_DWBC(dwbc_base) \
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container_of(dwbc_base, struct dcn10_dwbc, base)
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static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
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{
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if (caps) {
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caps->adapter_id = 0; /* we only support 1 adapter currently */
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caps->hw_version = DCN_VERSION_1_0;
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caps->num_pipes = 2;
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memset(&caps->reserved, 0, sizeof(caps->reserved));
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memset(&caps->reserved2, 0, sizeof(caps->reserved2));
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caps->sw_version = dwb_ver_1_0;
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caps->caps.support_dwb = true;
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caps->caps.support_ogam = false;
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caps->caps.support_wbscl = true;
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caps->caps.support_ocsc = false;
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return true;
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} else {
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return false;
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}
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}
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static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
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{
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struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
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/* disable first. */
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dwbc->funcs->disable(dwbc);
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/* disable power gating */
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REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
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DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
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WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
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REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
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return true;
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}
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static bool dwb1_disable(struct dwbc *dwbc)
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{
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struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
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/* disable CNV */
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REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
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/* disable WB */
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REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
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/* soft reset */
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REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
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REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
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/* enable power gating */
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REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
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DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
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WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
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return true;
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}
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const struct dwbc_funcs dcn10_dwbc_funcs = {
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.get_caps = dwb1_get_caps,
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.enable = dwb1_enable,
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.disable = dwb1_disable,
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.update = NULL,
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.set_stereo = NULL,
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.set_new_content = NULL,
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.set_warmup = NULL,
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.dwb_set_scaler = NULL,
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};
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void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
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struct dc_context *ctx,
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const struct dcn10_dwbc_registers *dwbc_regs,
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const struct dcn10_dwbc_shift *dwbc_shift,
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const struct dcn10_dwbc_mask *dwbc_mask,
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int inst)
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{
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dwbc10->base.ctx = ctx;
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dwbc10->base.inst = inst;
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dwbc10->base.funcs = &dcn10_dwbc_funcs;
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dwbc10->dwbc_regs = dwbc_regs;
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dwbc10->dwbc_shift = dwbc_shift;
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dwbc10->dwbc_mask = dwbc_mask;
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}
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#endif
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