395 lines
11 KiB
C
395 lines
11 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dcn10_opp.h"
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#include "reg_helper.h"
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#define REG(reg) \
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(oppn10->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
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#define CTX \
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oppn10->base.ctx
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/************* FORMATTER ************/
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/**
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* set_truncation
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* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
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* 2) enable truncation
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* 3) HW remove 12bit FMT support for DCE11 power saving reason.
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*/
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static void opp1_set_truncation(
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struct dcn10_opp *oppn10,
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const struct bit_depth_reduction_params *params)
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{
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED,
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FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH,
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FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
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}
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static void opp1_set_spatial_dither(
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struct dcn10_opp *oppn10,
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const struct bit_depth_reduction_params *params)
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{
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/*Disable spatial (random) dithering*/
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REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
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FMT_SPATIAL_DITHER_EN, 0,
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FMT_SPATIAL_DITHER_MODE, 0,
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FMT_SPATIAL_DITHER_DEPTH, 0,
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FMT_TEMPORAL_DITHER_EN, 0,
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FMT_HIGHPASS_RANDOM_ENABLE, 0,
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FMT_FRAME_RANDOM_ENABLE, 0,
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FMT_RGB_RANDOM_ENABLE, 0);
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/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
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if (params->flags.FRAME_RANDOM == 1) {
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if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) {
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REG_UPDATE_2(FMT_CONTROL,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
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} else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
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REG_UPDATE_2(FMT_CONTROL,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
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} else {
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return;
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}
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} else {
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REG_UPDATE_2(FMT_CONTROL,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
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}
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/*Set seed for random values for
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* spatial dithering for R,G,B channels*/
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REG_SET(FMT_DITHER_RAND_R_SEED, 0,
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FMT_RAND_R_SEED, params->r_seed_value);
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REG_SET(FMT_DITHER_RAND_G_SEED, 0,
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FMT_RAND_G_SEED, params->g_seed_value);
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REG_SET(FMT_DITHER_RAND_B_SEED, 0,
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FMT_RAND_B_SEED, params->b_seed_value);
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/* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero
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* offset for the R/Cr channel, lower 4LSB
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* is forced to zeros. Typically set to 0
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* RGB and 0x80000 YCbCr.
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*/
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/* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero
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* offset for the G/Y channel, lower 4LSB is
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* forced to zeros. Typically set to 0 RGB
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* and 0x80000 YCbCr.
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*/
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/* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero
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* offset for the B/Cb channel, lower 4LSB is
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* forced to zeros. Typically set to 0 RGB and
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* 0x80000 YCbCr.
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*/
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REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
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/*Enable spatial dithering*/
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FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED,
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/* Set spatial dithering mode
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* (default is Seed patterrn AAAA...)
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*/
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FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
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/*Set spatial dithering bit depth*/
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FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
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/*Disable High pass filter*/
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FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
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/*Reset only at startup*/
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FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
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/*Set RGB data dithered with x^28+x^3+1*/
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FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
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}
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void opp1_program_bit_depth_reduction(
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struct output_pixel_processor *opp,
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const struct bit_depth_reduction_params *params)
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{
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struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
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opp1_set_truncation(oppn10, params);
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opp1_set_spatial_dither(oppn10, params);
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/* TODO
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* set_temporal_dither(oppn10, params);
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*/
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}
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/**
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* set_pixel_encoding
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*
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* Set Pixel Encoding
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* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
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* 1: YCbCr 4:2:2
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*/
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static void opp1_set_pixel_encoding(
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struct dcn10_opp *oppn10,
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const struct clamping_and_pixel_encoding_params *params)
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{
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switch (params->pixel_encoding) {
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case PIXEL_ENCODING_RGB:
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case PIXEL_ENCODING_YCBCR444:
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REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
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break;
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case PIXEL_ENCODING_YCBCR422:
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REG_UPDATE_3(FMT_CONTROL,
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FMT_PIXEL_ENCODING, 1,
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FMT_SUBSAMPLING_MODE, 2,
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FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
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break;
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case PIXEL_ENCODING_YCBCR420:
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REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
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break;
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default:
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break;
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}
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}
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/**
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* Set Clamping
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* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
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* 1 for 8 bpc
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* 2 for 10 bpc
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* 3 for 12 bpc
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* 7 for programable
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* 2) Enable clamp if Limited range requested
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*/
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static void opp1_set_clamping(
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struct dcn10_opp *oppn10,
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const struct clamping_and_pixel_encoding_params *params)
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{
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REG_UPDATE_2(FMT_CLAMP_CNTL,
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FMT_CLAMP_DATA_EN, 0,
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FMT_CLAMP_COLOR_FORMAT, 0);
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switch (params->clamping_level) {
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case CLAMPING_FULL_RANGE:
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REG_UPDATE_2(FMT_CLAMP_CNTL,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 0);
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break;
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case CLAMPING_LIMITED_RANGE_8BPC:
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REG_UPDATE_2(FMT_CLAMP_CNTL,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 1);
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break;
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case CLAMPING_LIMITED_RANGE_10BPC:
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REG_UPDATE_2(FMT_CLAMP_CNTL,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 2);
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break;
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case CLAMPING_LIMITED_RANGE_12BPC:
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REG_UPDATE_2(FMT_CLAMP_CNTL,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 3);
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break;
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case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
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/* TODO */
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default:
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break;
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}
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}
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void opp1_set_dyn_expansion(
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struct output_pixel_processor *opp,
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enum dc_color_space color_sp,
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enum dc_color_depth color_dpth,
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enum signal_type signal)
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{
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struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
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REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
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FMT_DYNAMIC_EXP_EN, 0,
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FMT_DYNAMIC_EXP_MODE, 0);
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if (opp->dyn_expansion == DYN_EXPANSION_DISABLE)
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return;
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/*00 - 10-bit -> 12-bit dynamic expansion*/
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/*01 - 8-bit -> 12-bit dynamic expansion*/
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if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
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signal == SIGNAL_TYPE_DISPLAY_PORT ||
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signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
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signal == SIGNAL_TYPE_VIRTUAL) {
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switch (color_dpth) {
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case COLOR_DEPTH_888:
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REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
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FMT_DYNAMIC_EXP_EN, 1,
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FMT_DYNAMIC_EXP_MODE, 1);
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break;
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case COLOR_DEPTH_101010:
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REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
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FMT_DYNAMIC_EXP_EN, 1,
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FMT_DYNAMIC_EXP_MODE, 0);
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break;
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case COLOR_DEPTH_121212:
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REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
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FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
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FMT_DYNAMIC_EXP_MODE, 0);
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break;
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default:
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break;
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}
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}
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}
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static void opp1_program_clamping_and_pixel_encoding(
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struct output_pixel_processor *opp,
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const struct clamping_and_pixel_encoding_params *params)
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{
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struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
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opp1_set_clamping(oppn10, params);
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opp1_set_pixel_encoding(oppn10, params);
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}
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void opp1_program_fmt(
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struct output_pixel_processor *opp,
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struct bit_depth_reduction_params *fmt_bit_depth,
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struct clamping_and_pixel_encoding_params *clamping)
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{
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struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
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if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
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/* dithering is affected by <CrtcSourceSelect>, hence should be
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* programmed afterwards */
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opp1_program_bit_depth_reduction(
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opp,
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fmt_bit_depth);
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opp1_program_clamping_and_pixel_encoding(
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opp,
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clamping);
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return;
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}
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void opp1_program_stereo(
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struct output_pixel_processor *opp,
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bool enable,
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const struct dc_crtc_timing *timing)
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{
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struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
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uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;
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uint32_t space1_size = timing->v_total - timing->v_addressable;
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/* TODO: confirm computation of space2_size */
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uint32_t space2_size = timing->v_total - timing->v_addressable;
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if (!enable) {
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active_width = 0;
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space1_size = 0;
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space2_size = 0;
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}
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/* TODO: for which cases should FMT_STEREOSYNC_OVERRIDE be set? */
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REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
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REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);
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/* Program OPPBUF_3D_VACT_SPACE1_SIZE and OPPBUF_VACT_SPACE2_SIZE registers
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* In 3D progressive frames, Vactive space happens only in between the 2 frames,
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* so only need to program OPPBUF_3D_VACT_SPACE1_SIZE
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* In 3D alternative frames, left and right frames, top and bottom field.
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*/
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if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE)
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REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);
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else
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REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
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/* TODO: Is programming of OPPBUF_DUMMY_DATA_R/G/B needed? */
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/*
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REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
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OPPBUF_DUMMY_DATA_R, data_r);
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REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
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OPPBUF_DUMMY_DATA_G, data_g);
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REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
|
||
|
|
OPPBUF_DUMMY_DATA_B, _data_b);
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
|
||
|
|
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
|
||
|
|
{
|
||
|
|
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
|
||
|
|
uint32_t regval = enable ? 1 : 0;
|
||
|
|
|
||
|
|
REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************/
|
||
|
|
/* Constructor, Destructor */
|
||
|
|
/*****************************************/
|
||
|
|
|
||
|
|
void opp1_destroy(struct output_pixel_processor **opp)
|
||
|
|
{
|
||
|
|
kfree(TO_DCN10_OPP(*opp));
|
||
|
|
*opp = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct opp_funcs dcn10_opp_funcs = {
|
||
|
|
.opp_set_dyn_expansion = opp1_set_dyn_expansion,
|
||
|
|
.opp_program_fmt = opp1_program_fmt,
|
||
|
|
.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
|
||
|
|
.opp_program_stereo = opp1_program_stereo,
|
||
|
|
.opp_pipe_clock_control = opp1_pipe_clock_control,
|
||
|
|
.opp_set_disp_pattern_generator = NULL,
|
||
|
|
.opp_program_dpg_dimensions = NULL,
|
||
|
|
.dpg_is_blanked = NULL,
|
||
|
|
.opp_destroy = opp1_destroy
|
||
|
|
};
|
||
|
|
|
||
|
|
void dcn10_opp_construct(struct dcn10_opp *oppn10,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
uint32_t inst,
|
||
|
|
const struct dcn10_opp_registers *regs,
|
||
|
|
const struct dcn10_opp_shift *opp_shift,
|
||
|
|
const struct dcn10_opp_mask *opp_mask)
|
||
|
|
{
|
||
|
|
|
||
|
|
oppn10->base.ctx = ctx;
|
||
|
|
oppn10->base.inst = inst;
|
||
|
|
oppn10->base.funcs = &dcn10_opp_funcs;
|
||
|
|
|
||
|
|
oppn10->regs = regs;
|
||
|
|
oppn10->opp_shift = opp_shift;
|
||
|
|
oppn10->opp_mask = opp_mask;
|
||
|
|
}
|