325 lines
14 KiB
C
325 lines
14 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "resource.h"
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#include "mcif_wb.h"
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#include "dcn20_mmhubbub.h"
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#define REG(reg)\
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mcif_wb20->mcif_wb_regs->reg
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#define CTX \
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mcif_wb20->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name
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#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
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#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
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/* wbif programming guide:
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* 1. set up wbif parameter:
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* unsigned long long luma_address[4]; //4 frame buffer
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* unsigned long long chroma_address[4];
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* unsigned int luma_pitch;
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* unsigned int chroma_pitch;
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* unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10
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* unsigned int slice_lines; //slice size
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* unsigned int time_per_pixel; // time per pixel, in ns
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* unsigned int arbitration_slice; // 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes
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* unsigned int max_scaled_time; // used for QOS generation
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* unsigned int swlock=0x0;
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* unsigned int cli_watermark[4]; //4 group urgent watermark
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* unsigned int pstate_watermark[4]; //4 group pstate watermark
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* unsigned int sw_int_en; // Software interrupt enable, frame end and overflow
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* unsigned int sw_slice_int_en; // slice end interrupt enable
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* unsigned int sw_overrun_int_en; // overrun error interrupt enable
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* unsigned int vce_int_en; // VCE interrupt enable, frame end and overflow
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* unsigned int vce_slice_int_en; // VCE slice end interrupt enable, frame end and overflow
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*
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* 2. configure wbif register
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* a. call mmhubbub_config_wbif()
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*
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* 3. Enable wbif
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* call set_wbif_bufmgr_enable();
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*
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* 4. wbif_dump_status(), option, for debug purpose
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* the bufmgr status can show the progress of write back, can be used for debug purpose
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*/
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static void mmhubbub2_config_mcif_buf(struct mcif_wb *mcif_wb,
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struct mcif_buf_params *params,
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unsigned int dest_height)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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/* sw lock buffer0~buffer3, default is 0 */
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);
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/* buffer address for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
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REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
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/* right eye sub-buffer address offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0);
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/* buffer address for Chroma in planar mode (unused in packing mode) */
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REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
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REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
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/* right eye offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0);
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/* buffer address for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
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REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
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/* right eye sub-buffer address offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0);
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/* buffer address for Chroma in planar mode (unused in packing mode) */
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REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
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REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
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/* right eye offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0);
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/* buffer address for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
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REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
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/* right eye sub-buffer address offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0);
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/* buffer address for Chroma in planar mode (unused in packing mode) */
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REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
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REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
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/* right eye offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0);
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/* buffer address for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
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REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
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/* right eye sub-buffer address offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0);
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/* buffer address for Chroma in planar mode (unused in packing mode) */
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REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
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REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
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/* right eye offset for packing mode or Luma in planar mode */
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REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0);
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/* setup luma & chroma size
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* should be enough to contain a whole frame Luma data,
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* the programmed value is frame buffer size [27:8], 256-byte aligned
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*/
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REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
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REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
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/* enable address fence */
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
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/* setup pitch, the programmed value is [15:8], 256B align */
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REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
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MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8);
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/* Set pitch for MC cache warm up mode */
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/* Pitch is 256 bytes aligned. The default pitch is 4K */
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/* default is 0x10 */
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REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, params->warmup_pitch);
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}
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static void mmhubbub2_config_mcif_arb(struct mcif_wb *mcif_wb,
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struct mcif_arb_params *params)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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/* Programmed by the video driver based on the CRTC timing (for DWB) */
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REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
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/* Programming dwb watermark */
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/* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */
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/* Program in ns. A formula will be provided in the pseudo code to calculate the value. */
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REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
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/* urgent_watermarkA */
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REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]);
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REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
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/* urgent_watermarkB */
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REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]);
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REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
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/* urgent_watermarkC */
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REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]);
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REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
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/* urgent_watermarkD */
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REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]);
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/* Programming nb pstate watermark */
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/* nbp_state_change_watermarkA */
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REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
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REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
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NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]);
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/* nbp_state_change_watermarkB */
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REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
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REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
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NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]);
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/* nbp_state_change_watermarkC */
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REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
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REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
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NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]);
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/* nbp_state_change_watermarkD */
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REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
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REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
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NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]);
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/* max_scaled_time */
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REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
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/* slice_lines */
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REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
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/* Set arbitration unit for Luma/Chroma */
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/* arb_unit=2 should be chosen for more efficiency */
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/* Arbitration size, 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes */
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REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice);
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}
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void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
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struct mcif_irq_params *params)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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/* Set interrupt mask */
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en);
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en);
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, params->sw_overrun_int_en);
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REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en);
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if (mcif_wb20->mcif_wb_mask->MCIF_WB_BUFMGR_VCE_SLICE_INT_EN)
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REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en);
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}
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void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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/* Enable Mcifwb */
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1);
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}
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void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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/* disable buffer manager */
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REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0);
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}
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/* set which group of pstate watermark to use and set wbif watermark change request */
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/*
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static void mmhubbub2_wbif_watermark_change_req(struct mcif_wb *mcif_wb, unsigned int wm_set)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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uint32_t change_req;
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REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, &change_req);
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change_req = (change_req == 0) ? 1 : 0;
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REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, wm_set);
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REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, change_req);
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}
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*/
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/* Set watermark change interrupt disable bit */
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/*
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static void mmhubbub2_set_wbif_watermark_change_int_disable(struct mcif_wb *mcif_wb, unsigned int ack_int_dis)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, ack_int_dis);
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}
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*/
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/* Read watermark change interrupt status */
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/*
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unsigned int mmhubbub2_get_wbif_watermark_change_int_status(struct mcif_wb *mcif_wb)
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{
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struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
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uint32_t irq_status;
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||
|
|
|
||
|
|
REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, &irq_status);
|
||
|
|
return irq_status;
|
||
|
|
}
|
||
|
|
*/
|
||
|
|
|
||
|
|
void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
|
||
|
|
struct mcif_buf_params *mcif_params,
|
||
|
|
enum dwb_scaler_mode out_format,
|
||
|
|
unsigned int dest_width,
|
||
|
|
unsigned int dest_height,
|
||
|
|
struct mcif_wb_frame_dump_info *dump_info,
|
||
|
|
unsigned char *luma_buffer,
|
||
|
|
unsigned char *chroma_buffer,
|
||
|
|
unsigned char *dest_luma_buffer,
|
||
|
|
unsigned char *dest_chroma_buffer)
|
||
|
|
{
|
||
|
|
struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
|
||
|
|
|
||
|
|
REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);
|
||
|
|
|
||
|
|
memcpy(dest_luma_buffer, luma_buffer, mcif_params->luma_pitch * dest_height);
|
||
|
|
memcpy(dest_chroma_buffer, chroma_buffer, mcif_params->chroma_pitch * dest_height / 2);
|
||
|
|
|
||
|
|
REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);
|
||
|
|
|
||
|
|
dump_info->format = out_format;
|
||
|
|
dump_info->width = dest_width;
|
||
|
|
dump_info->height = dest_height;
|
||
|
|
dump_info->luma_pitch = mcif_params->luma_pitch;
|
||
|
|
dump_info->chroma_pitch = mcif_params->chroma_pitch;
|
||
|
|
dump_info->size = dest_height * (mcif_params->luma_pitch + mcif_params->chroma_pitch);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct mcif_wb_funcs dcn20_mmhubbub_funcs = {
|
||
|
|
.enable_mcif = mmhubbub2_enable_mcif,
|
||
|
|
.disable_mcif = mmhubbub2_disable_mcif,
|
||
|
|
.config_mcif_buf = mmhubbub2_config_mcif_buf,
|
||
|
|
.config_mcif_arb = mmhubbub2_config_mcif_arb,
|
||
|
|
.config_mcif_irq = mmhubbub2_config_mcif_irq,
|
||
|
|
.dump_frame = mcifwb2_dump_frame,
|
||
|
|
};
|
||
|
|
|
||
|
|
void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
const struct dcn20_mmhubbub_registers *mcif_wb_regs,
|
||
|
|
const struct dcn20_mmhubbub_shift *mcif_wb_shift,
|
||
|
|
const struct dcn20_mmhubbub_mask *mcif_wb_mask,
|
||
|
|
int inst)
|
||
|
|
{
|
||
|
|
mcif_wb20->base.ctx = ctx;
|
||
|
|
|
||
|
|
mcif_wb20->base.inst = inst;
|
||
|
|
mcif_wb20->base.funcs = &dcn20_mmhubbub_funcs;
|
||
|
|
|
||
|
|
mcif_wb20->mcif_wb_regs = mcif_wb_regs;
|
||
|
|
mcif_wb20->mcif_wb_shift = mcif_wb_shift;
|
||
|
|
mcif_wb20->mcif_wb_mask = mcif_wb_mask;
|
||
|
|
}
|