387 lines
9.9 KiB
C
387 lines
9.9 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dcn20_opp.h"
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#include "reg_helper.h"
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#define REG(reg) \
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(oppn20->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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oppn20->opp_shift->field_name, oppn20->opp_mask->field_name
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#define CTX \
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oppn20->base.ctx
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void opp2_set_disp_pattern_generator(
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struct output_pixel_processor *opp,
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enum controller_dp_test_pattern test_pattern,
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enum controller_dp_color_space color_space,
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enum dc_color_depth color_depth,
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const struct tg_color *solid_color,
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int width,
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int height,
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int offset)
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{
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struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
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enum test_pattern_color_format bit_depth;
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enum test_pattern_dyn_range dyn_range;
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enum test_pattern_mode mode;
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/* color ramp generator mixes 16-bits color */
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uint32_t src_bpc = 16;
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/* requested bpc */
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uint32_t dst_bpc;
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uint32_t index;
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/* RGB values of the color bars.
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* Produce two RGB colors: RGB0 - white (all Fs)
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* and RGB1 - black (all 0s)
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* (three RGB components for two colors)
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*/
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uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
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0x0000, 0x0000};
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/* dest color (converted to the specified color format) */
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uint16_t dst_color[6];
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uint32_t inc_base;
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/* translate to bit depth */
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switch (color_depth) {
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case COLOR_DEPTH_666:
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bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
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break;
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case COLOR_DEPTH_888:
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bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
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break;
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case COLOR_DEPTH_101010:
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bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
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break;
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case COLOR_DEPTH_121212:
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bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
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break;
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default:
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bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
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break;
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}
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/* set DPG dimentions */
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REG_SET_2(DPG_DIMENSIONS, 0,
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DPG_ACTIVE_WIDTH, width,
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DPG_ACTIVE_HEIGHT, height);
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/* set DPG offset */
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REG_SET_2(DPG_OFFSET_SEGMENT, 0,
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DPG_X_OFFSET, offset,
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DPG_SEGMENT_WIDTH, 0);
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switch (test_pattern) {
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case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
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case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
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{
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dyn_range = (test_pattern ==
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CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
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TEST_PATTERN_DYN_RANGE_CEA :
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TEST_PATTERN_DYN_RANGE_VESA);
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switch (color_space) {
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case CONTROLLER_DP_COLOR_SPACE_YCBCR601:
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mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR601;
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break;
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case CONTROLLER_DP_COLOR_SPACE_YCBCR709:
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mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR709;
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break;
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case CONTROLLER_DP_COLOR_SPACE_RGB:
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default:
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mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
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break;
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}
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REG_UPDATE_6(DPG_CONTROL,
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DPG_EN, 1,
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DPG_MODE, mode,
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DPG_DYNAMIC_RANGE, dyn_range,
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DPG_BIT_DEPTH, bit_depth,
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DPG_VRES, 6,
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DPG_HRES, 6);
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}
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break;
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case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
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case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
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{
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mode = (test_pattern ==
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CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
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TEST_PATTERN_MODE_VERTICALBARS :
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TEST_PATTERN_MODE_HORIZONTALBARS);
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switch (bit_depth) {
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case TEST_PATTERN_COLOR_FORMAT_BPC_6:
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dst_bpc = 6;
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break;
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case TEST_PATTERN_COLOR_FORMAT_BPC_8:
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dst_bpc = 8;
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break;
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case TEST_PATTERN_COLOR_FORMAT_BPC_10:
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dst_bpc = 10;
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break;
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default:
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dst_bpc = 8;
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break;
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}
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/* adjust color to the required colorFormat */
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for (index = 0; index < 6; index++) {
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/* dst = 2^dstBpc * src / 2^srcBpc = src >>
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* (srcBpc - dstBpc);
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*/
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dst_color[index] =
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src_color[index] >> (src_bpc - dst_bpc);
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/* DPG_COLOUR registers are 16-bit MSB aligned value with bits 3:0 hardwired to ZERO.
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* XXXXXXXXXX000000 for 10 bit,
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* XXXXXXXX00000000 for 8 bit,
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* XXXXXX0000000000 for 6 bits
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*/
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dst_color[index] <<= (16 - dst_bpc);
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}
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REG_SET_2(DPG_COLOUR_R_CR, 0,
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DPG_COLOUR1_R_CR, dst_color[0],
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DPG_COLOUR0_R_CR, dst_color[3]);
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REG_SET_2(DPG_COLOUR_G_Y, 0,
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DPG_COLOUR1_G_Y, dst_color[1],
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DPG_COLOUR0_G_Y, dst_color[4]);
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REG_SET_2(DPG_COLOUR_B_CB, 0,
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DPG_COLOUR1_B_CB, dst_color[2],
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DPG_COLOUR0_B_CB, dst_color[5]);
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/* enable test pattern */
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REG_UPDATE_6(DPG_CONTROL,
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DPG_EN, 1,
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DPG_MODE, mode,
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DPG_DYNAMIC_RANGE, 0,
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DPG_BIT_DEPTH, bit_depth,
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DPG_VRES, 0,
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DPG_HRES, 0);
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}
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break;
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case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
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{
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mode = (bit_depth ==
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TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
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TEST_PATTERN_MODE_DUALRAMP_RGB :
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TEST_PATTERN_MODE_SINGLERAMP_RGB);
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switch (bit_depth) {
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case TEST_PATTERN_COLOR_FORMAT_BPC_6:
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dst_bpc = 6;
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break;
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case TEST_PATTERN_COLOR_FORMAT_BPC_8:
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dst_bpc = 8;
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break;
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case TEST_PATTERN_COLOR_FORMAT_BPC_10:
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dst_bpc = 10;
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break;
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default:
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dst_bpc = 8;
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break;
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}
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/* increment for the first ramp for one color gradation
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* 1 gradation for 6-bit color is 2^10
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* gradations in 16-bit color
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*/
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inc_base = (src_bpc - dst_bpc);
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switch (bit_depth) {
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case TEST_PATTERN_COLOR_FORMAT_BPC_6:
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{
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REG_SET_3(DPG_RAMP_CONTROL, 0,
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DPG_RAMP0_OFFSET, 0,
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DPG_INC0, inc_base,
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DPG_INC1, 0);
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REG_UPDATE_2(DPG_CONTROL,
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DPG_VRES, 6,
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DPG_HRES, 6);
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}
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break;
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case TEST_PATTERN_COLOR_FORMAT_BPC_8:
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{
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REG_SET_3(DPG_RAMP_CONTROL, 0,
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DPG_RAMP0_OFFSET, 0,
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DPG_INC0, inc_base,
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DPG_INC1, 0);
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REG_UPDATE_2(DPG_CONTROL,
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DPG_VRES, 6,
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DPG_HRES, 8);
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}
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break;
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case TEST_PATTERN_COLOR_FORMAT_BPC_10:
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{
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REG_SET_3(DPG_RAMP_CONTROL, 0,
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DPG_RAMP0_OFFSET, 384 << 6,
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DPG_INC0, inc_base,
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DPG_INC1, inc_base + 2);
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REG_UPDATE_2(DPG_CONTROL,
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DPG_VRES, 5,
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DPG_HRES, 8);
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}
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break;
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default:
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break;
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}
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/* enable test pattern */
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REG_UPDATE_4(DPG_CONTROL,
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DPG_EN, 1,
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DPG_MODE, mode,
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DPG_DYNAMIC_RANGE, 0,
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DPG_BIT_DEPTH, bit_depth);
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}
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break;
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case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
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{
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REG_WRITE(DPG_CONTROL, 0);
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REG_WRITE(DPG_COLOUR_R_CR, 0);
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REG_WRITE(DPG_COLOUR_G_Y, 0);
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REG_WRITE(DPG_COLOUR_B_CB, 0);
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REG_WRITE(DPG_RAMP_CONTROL, 0);
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}
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break;
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case CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR:
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{
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opp2_dpg_set_blank_color(opp, solid_color);
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REG_UPDATE_2(DPG_CONTROL,
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DPG_EN, 1,
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DPG_MODE, TEST_PATTERN_MODE_HORIZONTALBARS);
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REG_SET_2(DPG_DIMENSIONS, 0,
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DPG_ACTIVE_WIDTH, width,
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DPG_ACTIVE_HEIGHT, height);
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}
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break;
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default:
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break;
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}
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}
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void opp2_program_dpg_dimensions(
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struct output_pixel_processor *opp,
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int width, int height)
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{
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struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
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REG_SET_2(DPG_DIMENSIONS, 0,
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DPG_ACTIVE_WIDTH, width,
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DPG_ACTIVE_HEIGHT, height);
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}
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void opp2_dpg_set_blank_color(
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struct output_pixel_processor *opp,
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const struct tg_color *color)
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{
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struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
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/* 16-bit MSB aligned value. Bits 3:0 of this field are hardwired to ZERO */
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ASSERT(color);
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REG_SET_2(DPG_COLOUR_B_CB, 0,
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DPG_COLOUR1_B_CB, color->color_b_cb << 6,
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DPG_COLOUR0_B_CB, color->color_b_cb << 6);
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REG_SET_2(DPG_COLOUR_G_Y, 0,
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DPG_COLOUR1_G_Y, color->color_g_y << 6,
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DPG_COLOUR0_G_Y, color->color_g_y << 6);
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REG_SET_2(DPG_COLOUR_R_CR, 0,
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DPG_COLOUR1_R_CR, color->color_r_cr << 6,
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DPG_COLOUR0_R_CR, color->color_r_cr << 6);
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}
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bool opp2_dpg_is_blanked(struct output_pixel_processor *opp)
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{
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struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
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uint32_t dpg_en, dpg_mode;
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uint32_t double_buffer_pending;
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REG_GET_2(DPG_CONTROL,
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DPG_EN, &dpg_en,
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DPG_MODE, &dpg_mode);
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REG_GET(DPG_STATUS,
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DPG_DOUBLE_BUFFER_PENDING, &double_buffer_pending);
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return (dpg_en == 1) &&
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(double_buffer_pending == 0);
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}
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void opp2_program_left_edge_extra_pixel (
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struct output_pixel_processor *opp,
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bool count)
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{
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struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
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/* Specifies the number of extra left edge pixels that are supplied to
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* the 422 horizontal chroma sub-sample filter.
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* Note that when left edge pixel is not "0", fmt pixel encoding can be in either 420 or 422 mode
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* */
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REG_UPDATE(FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, count);
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}
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/*****************************************/
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/* Constructor, Destructor */
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/*****************************************/
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static struct opp_funcs dcn20_opp_funcs = {
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.opp_set_dyn_expansion = opp1_set_dyn_expansion,
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.opp_program_fmt = opp1_program_fmt,
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.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
|
||
|
|
.opp_program_stereo = opp1_program_stereo,
|
||
|
|
.opp_pipe_clock_control = opp1_pipe_clock_control,
|
||
|
|
.opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator,
|
||
|
|
.opp_program_dpg_dimensions = opp2_program_dpg_dimensions,
|
||
|
|
.dpg_is_blanked = opp2_dpg_is_blanked,
|
||
|
|
.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
|
||
|
|
.opp_destroy = opp1_destroy,
|
||
|
|
.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,
|
||
|
|
};
|
||
|
|
|
||
|
|
void dcn20_opp_construct(struct dcn20_opp *oppn20,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
uint32_t inst,
|
||
|
|
const struct dcn20_opp_registers *regs,
|
||
|
|
const struct dcn20_opp_shift *opp_shift,
|
||
|
|
const struct dcn20_opp_mask *opp_mask)
|
||
|
|
{
|
||
|
|
oppn20->base.ctx = ctx;
|
||
|
|
oppn20->base.inst = inst;
|
||
|
|
oppn20->base.funcs = &dcn20_opp_funcs;
|
||
|
|
|
||
|
|
oppn20->regs = regs;
|
||
|
|
oppn20->opp_shift = opp_shift;
|
||
|
|
oppn20->opp_mask = opp_mask;
|
||
|
|
}
|
||
|
|
|