84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
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/* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCN201_DPP_H__
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#define __DCN201_DPP_H__
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#include "dcn20/dcn20_dpp.h"
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#define TO_DCN201_DPP(dpp)\
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container_of(dpp, struct dcn201_dpp, base)
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#define TF_REG_LIST_DCN201(id) \
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TF_REG_LIST_DCN20(id)
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#define TF_REG_LIST_SH_MASK_DCN201(mask_sh)\
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TF_REG_LIST_SH_MASK_DCN20(mask_sh)
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#define TF_REG_FIELD_LIST_DCN201(type) \
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TF_REG_FIELD_LIST_DCN2_0(type)
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struct dcn201_dpp_shift {
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TF_REG_FIELD_LIST_DCN201(uint8_t);
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};
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struct dcn201_dpp_mask {
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TF_REG_FIELD_LIST_DCN201(uint32_t);
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};
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#define DPP_DCN201_REG_VARIABLE_LIST \
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DPP_DCN2_REG_VARIABLE_LIST
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struct dcn201_dpp_registers {
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DPP_DCN201_REG_VARIABLE_LIST;
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};
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struct dcn201_dpp {
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struct dpp base;
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const struct dcn201_dpp_registers *tf_regs;
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const struct dcn201_dpp_shift *tf_shift;
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const struct dcn201_dpp_mask *tf_mask;
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const uint16_t *filter_v;
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const uint16_t *filter_h;
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const uint16_t *filter_v_c;
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const uint16_t *filter_h_c;
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int lb_pixel_depth_supported;
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int lb_memory_size;
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int lb_bits_per_entry;
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bool is_write_to_ram_a_safe;
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struct scaler_data scl_data;
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struct pwl_params pwl_data;
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};
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bool dpp201_construct(struct dcn201_dpp *dpp2,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn201_dpp_registers *tf_regs,
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const struct dcn201_dpp_shift *tf_shift,
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const struct dcn201_dpp_mask *tf_mask);
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#endif /* __DC_HWSS_DCN201_H__ */
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