204 lines
6.7 KiB
C
204 lines
6.7 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "dcn201_optc.h"
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#include "dcn10/dcn10_optc.h"
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#include "dc.h"
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#define REG(reg)\
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optc1->tg_regs->reg
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#define CTX \
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optc1->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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optc1->tg_shift->field_name, optc1->tg_mask->field_name
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/*TEMP: Need to figure out inheritance model here.*/
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bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
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{
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return optc1_is_two_pixels_per_containter(timing);
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}
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static void optc201_triplebuffer_lock(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_SET(OTG_GLOBAL_CONTROL0, 0,
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OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
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REG_SET(OTG_VUPDATE_KEEPOUT, 0,
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OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
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REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
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OTG_MASTER_UPDATE_LOCK, 1);
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if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
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REG_WAIT(OTG_MASTER_UPDATE_LOCK,
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UPDATE_LOCK_STATUS, 1,
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1, 10);
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}
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static void optc201_triplebuffer_unlock(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
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OTG_MASTER_UPDATE_LOCK, 0);
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REG_SET(OTG_VUPDATE_KEEPOUT, 0,
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OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
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}
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static bool optc201_validate_timing(
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struct timing_generator *optc,
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const struct dc_crtc_timing *timing)
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{
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uint32_t v_blank;
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uint32_t h_blank;
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uint32_t min_v_blank;
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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ASSERT(timing != NULL);
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v_blank = (timing->v_total - timing->v_addressable -
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timing->v_border_top - timing->v_border_bottom);
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h_blank = (timing->h_total - timing->h_addressable -
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timing->h_border_right -
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timing->h_border_left);
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if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
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timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
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timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
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timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
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timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
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timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
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return false;
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/* Check maximum number of pixels supported by Timing Generator
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* (Currently will never fail, in order to fail needs display which
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* needs more than 8192 horizontal and
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* more than 8192 vertical total pixels)
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*/
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if (timing->h_total > optc1->max_h_total ||
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timing->v_total > optc1->max_v_total)
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return false;
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if (h_blank < optc1->min_h_blank)
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return false;
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if (timing->h_sync_width < optc1->min_h_sync_width ||
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timing->v_sync_width < optc1->min_v_sync_width)
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return false;
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min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
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if (v_blank < min_v_blank)
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return false;
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return true;
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}
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static void optc201_get_optc_source(struct timing_generator *optc,
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uint32_t *num_of_src_opp,
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uint32_t *src_opp_id_0,
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uint32_t *src_opp_id_1)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_GET(OPTC_DATA_SOURCE_SELECT,
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OPTC_SEG0_SRC_SEL, src_opp_id_0);
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*num_of_src_opp = 1;
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}
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static struct timing_generator_funcs dcn201_tg_funcs = {
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.validate_timing = optc201_validate_timing,
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.program_timing = optc1_program_timing,
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.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
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.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
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.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
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.program_global_sync = optc1_program_global_sync,
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.enable_crtc = optc2_enable_crtc,
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.disable_crtc = optc1_disable_crtc,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.is_counter_moving = optc1_is_counter_moving,
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.get_position = optc1_get_position,
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.get_frame_count = optc1_get_vblank_counter,
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.get_scanoutpos = optc1_get_crtc_scanoutpos,
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.get_otg_active_size = optc1_get_otg_active_size,
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.set_early_control = optc1_set_early_control,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.wait_for_state = optc1_wait_for_state,
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.set_blank = optc1_set_blank,
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.is_blanked = optc1_is_blanked,
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.set_blank_color = optc1_program_blank_color,
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.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
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.enable_reset_trigger = optc1_enable_reset_trigger,
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.enable_crtc_reset = optc1_enable_crtc_reset,
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.disable_reset_trigger = optc1_disable_reset_trigger,
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.triplebuffer_lock = optc201_triplebuffer_lock,
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.triplebuffer_unlock = optc201_triplebuffer_unlock,
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.lock = optc1_lock,
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.unlock = optc1_unlock,
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.enable_optc_clock = optc1_enable_optc_clock,
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.set_drr = optc1_set_drr,
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.get_last_used_drr_vtotal = NULL,
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.set_vtotal_min_max = optc1_set_vtotal_min_max,
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.set_static_screen_control = optc1_set_static_screen_control,
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.program_stereo = optc1_program_stereo,
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.is_stereo_left_eye = optc1_is_stereo_left_eye,
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.set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
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.tg_init = optc1_tg_init,
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.is_tg_enabled = optc1_is_tg_enabled,
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.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
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.clear_optc_underflow = optc1_clear_optc_underflow,
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.get_crc = optc1_get_crc,
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.configure_crc = optc2_configure_crc,
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.set_dsc_config = optc2_set_dsc_config,
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.set_dwb_source = NULL,
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.get_optc_source = optc201_get_optc_source,
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.set_vtg_params = optc1_set_vtg_params,
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.program_manual_trigger = optc2_program_manual_trigger,
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.setup_manual_trigger = optc2_setup_manual_trigger,
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.get_hw_timing = optc1_get_hw_timing,
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};
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void dcn201_timing_generator_init(struct optc *optc1)
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{
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optc1->base.funcs = &dcn201_tg_funcs;
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optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
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optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
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optc1->min_h_blank = 32;
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optc1->min_v_blank = 3;
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optc1->min_v_blank_interlace = 5;
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optc1->min_h_sync_width = 8;
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optc1->min_v_sync_width = 1;
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}
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