247 lines
8.0 KiB
C
247 lines
8.0 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dm_helpers.h"
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#include "core_types.h"
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#include "resource.h"
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#include "dce/dce_hwseq.h"
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#include "dce110/dce110_hw_sequencer.h"
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#include "dcn21_hwseq.h"
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#include "vmid.h"
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#include "reg_helper.h"
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#include "hw/clk_mgr.h"
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#include "dc_dmub_srv.h"
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#include "abm.h"
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#include "link.h"
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#define DC_LOGGER_INIT(logger)
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#define CTX \
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hws->ctx
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#define REG(reg)\
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hws->regs->reg
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#undef FN
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#define FN(reg_name, field_name) \
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hws->shifts->field_name, hws->masks->field_name
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/* Temporary read settings, future will get values from kmd directly */
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static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,
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struct dce_hwseq *hws)
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{
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uint32_t page_table_base_hi;
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uint32_t page_table_base_lo;
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REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
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PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi);
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REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo);
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config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;
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}
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int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
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{
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struct dcn_hubbub_phys_addr_config config;
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config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
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config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
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config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
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config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
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config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
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config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
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config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
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config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
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config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
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mmhub_update_page_table_config(&config, hws);
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return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
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}
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// work around for Renoir s0i3, if register is programmed, bypass golden init.
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bool dcn21_s0i3_golden_init_wa(struct dc *dc)
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{
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struct dce_hwseq *hws = dc->hwseq;
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uint32_t value = 0;
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value = REG_READ(MICROSECOND_TIME_BASE_DIV);
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return value != 0x00120464;
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}
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void dcn21_exit_optimized_pwr_state(
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const struct dc *dc,
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struct dc_state *context)
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{
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dc->clk_mgr->funcs->update_clocks(
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dc->clk_mgr,
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context,
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false);
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}
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void dcn21_optimize_pwr_state(
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const struct dc *dc,
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struct dc_state *context)
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{
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dc->clk_mgr->funcs->update_clocks(
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dc->clk_mgr,
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context,
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true);
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}
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/* If user hotplug a HDMI monitor while in monitor off,
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* OS will do a mode set (with output timing) but keep output off.
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* In this case DAL will ask vbios to power up the pll in the PHY.
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* If user unplug the monitor (while we are on monitor off) or
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* system attempt to enter modern standby (which we will disable PLL),
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* PHY will hang on the next mode set attempt.
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* if enable PLL follow by disable PLL (without executing lane enable/disable),
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* RDPCS_PHY_DP_MPLLB_STATE remains 1,
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* which indicate that PLL disable attempt actually didn't go through.
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* As a workaround, insert PHY lane enable/disable before PLL disable.
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*/
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void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)
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{
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if (!pipe_ctx->stream->dpms_off)
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return;
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pipe_ctx->stream->dpms_off = false;
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link_set_dpms_on(context, pipe_ctx);
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link_set_dpms_off(pipe_ctx);
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pipe_ctx->stream->dpms_off = true;
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}
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static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = abm->ctx;
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uint32_t ramping_boundary = 0xFFFF;
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memset(&cmd, 0, sizeof(cmd));
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cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
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cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
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cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
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cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;
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cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;
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cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
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cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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return true;
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}
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void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
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{
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struct abm *abm = pipe_ctx->stream_res.abm;
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uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
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struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
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struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;
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if (dmcu) {
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dce110_set_abm_immediate_disable(pipe_ctx);
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return;
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}
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if (abm && panel_cntl) {
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dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,
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panel_cntl->inst);
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panel_cntl->funcs->store_backlight_level(panel_cntl);
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}
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}
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void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)
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{
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struct abm *abm = pipe_ctx->stream_res.abm;
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uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
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struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
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struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;
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if (dmcu) {
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dce110_set_pipe(pipe_ctx);
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return;
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}
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if (abm && panel_cntl)
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dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst);
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}
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bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
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uint32_t backlight_pwm_u16_16,
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uint32_t frame_ramp)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = pipe_ctx->stream->ctx;
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struct abm *abm = pipe_ctx->stream_res.abm;
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uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
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struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
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if (dc->dc->res_pool->dmcu) {
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dce110_set_backlight_level(pipe_ctx, backlight_pwm_u16_16, frame_ramp);
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return true;
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}
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if (abm && panel_cntl)
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dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst);
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memset(&cmd, 0, sizeof(cmd));
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cmd.abm_set_backlight.header.type = DMUB_CMD__ABM;
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cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
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cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;
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cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16;
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cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
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cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_cntl->inst);
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cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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return true;
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}
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bool dcn21_is_abm_supported(struct dc *dc,
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struct dc_state *context, struct dc_stream_state *stream)
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{
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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if (pipe_ctx->stream == stream &&
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(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
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return true;
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}
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return false;
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}
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