265 lines
8.0 KiB
C
265 lines
8.0 KiB
C
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "resource.h"
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#include "dwb.h"
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#include "dcn30_dwb.h"
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#define REG(reg)\
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dwbc30->dwbc_regs->reg
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#define CTX \
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dwbc30->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
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#define DC_LOGGER \
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dwbc30->base.ctx->logger
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static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
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{
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if (caps) {
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caps->adapter_id = 0; /* we only support 1 adapter currently */
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caps->hw_version = DCN_VERSION_3_0;
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caps->num_pipes = 2;
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memset(&caps->reserved, 0, sizeof(caps->reserved));
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memset(&caps->reserved2, 0, sizeof(caps->reserved2));
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caps->sw_version = dwb_ver_2_0;
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caps->caps.support_dwb = true;
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caps->caps.support_ogam = true;
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caps->caps.support_wbscl = true;
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caps->caps.support_ocsc = false;
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caps->caps.support_stereo = true;
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return true;
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} else {
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return false;
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}
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}
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void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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/* Set DWB source size */
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REG_UPDATE_2(FC_SOURCE_SIZE, FC_SOURCE_WIDTH, params->cnv_params.src_width,
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FC_SOURCE_HEIGHT, params->cnv_params.src_height);
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/* source size is not equal the source size, then enable cropping. */
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if (params->cnv_params.crop_en) {
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REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1);
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REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x);
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REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y);
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REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width);
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REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height);
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} else {
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REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0);
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}
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/* Set CAPTURE_RATE */
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REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate);
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dwb3_set_stereo(dwbc, ¶ms->stereo_params);
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}
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bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);
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/* Set WB_ENABLE (not double buffered; capture not enabled) */
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REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1);
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/* Set FC parameters */
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dwb3_config_fc(dwbc, params);
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/* Program color processing unit */
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dwb3_program_hdr_mult(dwbc, params);
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dwb3_set_gamut_remap(dwbc, params);
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dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);
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/* Program output denorm */
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dwb3_set_denorm(dwbc, params);
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/* Enable DWB capture enable (double buffered) */
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REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);
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/* First pixel count */
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REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96);
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return true;
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}
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bool dwb3_disable(struct dwbc *dwbc)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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/* disable FC */
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REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);
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/* disable WB */
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REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 0);
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DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);
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return true;
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}
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bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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unsigned int pre_locked;
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/*
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* Check if the caller has already locked DWB registers.
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* If so: assume the caller will unlock, so don't touch the lock.
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* If not: lock them for this update, then unlock after the
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* update is complete.
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*/
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REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked);
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DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);
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if (pre_locked == 0) {
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/* Lock DWB registers */
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REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 1);
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}
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/* Set FC parameters */
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dwb3_config_fc(dwbc, params);
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/* Program color processing unit */
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dwb3_program_hdr_mult(dwbc, params);
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dwb3_set_gamut_remap(dwbc, params);
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dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);
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/* Program output denorm */
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dwb3_set_denorm(dwbc, params);
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if (pre_locked == 0) {
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/* Unlock DWB registers */
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REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 0);
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}
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return true;
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}
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bool dwb3_is_enabled(struct dwbc *dwbc)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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unsigned int dwb_enabled = 0;
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unsigned int fc_frame_capture_en = 0;
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REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled);
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REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en);
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return ((dwb_enabled != 0) && (fc_frame_capture_en != 0));
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}
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void dwb3_set_stereo(struct dwbc *dwbc,
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struct dwb_stereo_params *stereo_params)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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if (stereo_params->stereo_enabled) {
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REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, stereo_params->stereo_eye_select);
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REG_UPDATE(FC_MODE_CTRL, FC_STEREO_EYE_POLARITY, stereo_params->stereo_polarity);
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DC_LOG_DWB("%s dwb stereo enabled", __func__);
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} else {
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REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, 0);
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DC_LOG_DWB("%s dwb stereo disabled", __func__);
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}
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}
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void dwb3_set_new_content(struct dwbc *dwbc,
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bool is_new_content)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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REG_UPDATE(FC_MODE_CTRL, FC_NEW_CONTENT, is_new_content);
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}
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void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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/* Set output format*/
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REG_UPDATE(DWB_OUT_CTRL, OUT_FORMAT, params->cnv_params.fc_out_format);
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/* Set output denorm */
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if (params->cnv_params.fc_out_format == DWB_OUT_FORMAT_32BPP_ARGB ||
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params->cnv_params.fc_out_format == DWB_OUT_FORMAT_32BPP_RGBA) {
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REG_UPDATE(DWB_OUT_CTRL, OUT_DENORM, params->cnv_params.out_denorm_mode);
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REG_UPDATE(DWB_OUT_CTRL, OUT_MAX, params->cnv_params.out_max_pix_val);
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REG_UPDATE(DWB_OUT_CTRL, OUT_MIN, params->cnv_params.out_min_pix_val);
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}
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}
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const struct dwbc_funcs dcn30_dwbc_funcs = {
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.get_caps = dwb3_get_caps,
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.enable = dwb3_enable,
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.disable = dwb3_disable,
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.update = dwb3_update,
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.is_enabled = dwb3_is_enabled,
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.set_stereo = dwb3_set_stereo,
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.set_new_content = dwb3_set_new_content,
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.dwb_program_output_csc = NULL,
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.dwb_ogam_set_input_transfer_func = dwb3_ogam_set_input_transfer_func, //TODO: rename
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.dwb_set_scaler = NULL,
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};
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void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,
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struct dc_context *ctx,
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const struct dcn30_dwbc_registers *dwbc_regs,
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const struct dcn30_dwbc_shift *dwbc_shift,
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const struct dcn30_dwbc_mask *dwbc_mask,
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int inst)
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{
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dwbc30->base.ctx = ctx;
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dwbc30->base.inst = inst;
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dwbc30->base.funcs = &dcn30_dwbc_funcs;
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dwbc30->dwbc_regs = dwbc_regs;
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dwbc30->dwbc_shift = dwbc_shift;
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dwbc30->dwbc_mask = dwbc_mask;
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}
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void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay)
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{
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struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
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/*
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* Set maximum delay of host read access to DWBSCL LUT or OGAM LUT if there are no
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* idle cycles in HW pipeline (in number of clock cycles times 4)
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*/
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REG_UPDATE(DWB_HOST_READ_CONTROL, DWB_HOST_READ_RATE_CONTROL, host_read_delay);
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DC_LOG_DWB("%s dwb3_rate_control at inst = %d", __func__, dwbc->inst);
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}
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