337 lines
10 KiB
C
337 lines
10 KiB
C
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dcn32_optc.h"
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#include "dcn30/dcn30_optc.h"
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#include "dcn31/dcn31_optc.h"
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#include "reg_helper.h"
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#include "dc.h"
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#include "dcn_calc_math.h"
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#include "dc_dmub_srv.h"
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#define REG(reg)\
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optc1->tg_regs->reg
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#define CTX \
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optc1->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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optc1->tg_shift->field_name, optc1->tg_mask->field_name
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static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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struct dc_crtc_timing *timing)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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uint32_t memory_mask = 0;
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int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
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int mpcc_hactive = h_active / opp_cnt;
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/* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
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int odm_mem_count = (h_active + 2047) / 2048;
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/*
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* display <= 4k : 2 memories + 2 pipes
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* 4k < display <= 8k : 4 memories + 2 pipes
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* 8k < display <= 12k : 6 memories + 4 pipes
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*/
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if (opp_cnt == 4) {
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if (odm_mem_count <= 2)
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memory_mask = 0x3;
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else if (odm_mem_count <= 4)
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memory_mask = 0xf;
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else
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memory_mask = 0x3f;
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} else {
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if (odm_mem_count <= 2)
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memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
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else if (odm_mem_count <= 4)
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memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
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else
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memory_mask = 0x77;
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}
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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OPTC_MEM_SEL, memory_mask);
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if (opp_cnt == 2) {
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REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 1,
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OPTC_SEG0_SRC_SEL, opp_id[0],
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OPTC_SEG1_SRC_SEL, opp_id[1]);
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} else if (opp_cnt == 4) {
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REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 3,
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OPTC_SEG0_SRC_SEL, opp_id[0],
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OPTC_SEG1_SRC_SEL, opp_id[1],
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OPTC_SEG2_SRC_SEL, opp_id[2],
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OPTC_SEG3_SRC_SEL, opp_id[3]);
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}
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REG_UPDATE(OPTC_WIDTH_CONTROL,
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OPTC_SEGMENT_WIDTH, mpcc_hactive);
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
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optc1->opp_count = opp_cnt;
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}
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static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
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}
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/**
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* Enable CRTC
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* Enable CRTC - call ASIC Control Object to enable Timing generator.
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*/
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static bool optc32_enable_crtc(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
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REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
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OPTC_SEG0_SRC_SEL, optc->inst);
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/* VTG enable first is for HW workaround */
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REG_UPDATE(CONTROL,
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VTG0_ENABLE, 1);
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REG_SEQ_START();
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/* Enable CRTC */
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REG_UPDATE_2(OTG_CONTROL,
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OTG_DISABLE_POINT_CNTL, 2,
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OTG_MASTER_EN, 1);
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REG_SEQ_SUBMIT();
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REG_SEQ_WAIT_DONE();
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return true;
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}
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/* disable_crtc */
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static bool optc32_disable_crtc(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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/* disable otg request until end of the first line
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* in the vertical blank region
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*/
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REG_UPDATE(OTG_CONTROL,
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OTG_MASTER_EN, 0);
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REG_UPDATE(CONTROL,
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VTG0_ENABLE, 0);
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/* CRTC disabled, so disable clock. */
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REG_WAIT(OTG_CLOCK_CONTROL,
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OTG_BUSY, 0,
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1, 150000);
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return true;
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}
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static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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/* Disable immediately. */
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REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
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/* CRTC disabled, so disable clock. */
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REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
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}
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static void optc32_disable_phantom_otg(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
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}
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static void optc32_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
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REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 0,
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OPTC_SEG0_SRC_SEL, optc->inst,
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OPTC_SEG1_SRC_SEL, 0xf,
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OPTC_SEG2_SRC_SEL, 0xf,
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OPTC_SEG3_SRC_SEL, 0xf
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);
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h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE, h_div);
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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OPTC_MEM_SEL, 0);
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optc1->opp_count = 1;
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}
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static void optc32_setup_manual_trigger(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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struct dc *dc = optc->ctx->dc;
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if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
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dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
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else {
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/*
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* MIN_MASK_EN is gone and MASK is now always enabled.
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*
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* To get it to it work with manual trigger we need to make sure
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* we program the correct bit.
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*/
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REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
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OTG_V_TOTAL_MIN_SEL, 1,
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OTG_V_TOTAL_MAX_SEL, 1,
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OTG_FORCE_LOCK_ON_EVENT, 0,
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OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
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// Setup manual flow control for EOF via TRIG_A
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optc->funcs->setup_manual_trigger(optc);
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}
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}
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static void optc32_set_drr(
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struct timing_generator *optc,
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const struct drr_params *params)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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if (params != NULL &&
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params->vertical_total_max > 0 &&
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params->vertical_total_min > 0) {
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if (params->vertical_total_mid != 0) {
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REG_SET(OTG_V_TOTAL_MID, 0,
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OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
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REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
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OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
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OTG_VTOTAL_MID_FRAME_NUM,
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(uint8_t)params->vertical_total_mid_frame_num);
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}
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optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
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optc32_setup_manual_trigger(optc);
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} else {
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REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
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OTG_SET_V_TOTAL_MIN_MASK, 0,
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OTG_V_TOTAL_MIN_SEL, 0,
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OTG_V_TOTAL_MAX_SEL, 0,
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OTG_FORCE_LOCK_ON_EVENT, 0);
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optc->funcs->set_vtotal_min_max(optc, 0, 0);
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}
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}
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static struct timing_generator_funcs dcn32_tg_funcs = {
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.validate_timing = optc1_validate_timing,
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.program_timing = optc1_program_timing,
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.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
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.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
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.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
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.program_global_sync = optc1_program_global_sync,
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.enable_crtc = optc32_enable_crtc,
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.disable_crtc = optc32_disable_crtc,
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.phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
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.disable_phantom_crtc = optc32_disable_phantom_otg,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.is_counter_moving = optc1_is_counter_moving,
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.get_position = optc1_get_position,
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.get_frame_count = optc1_get_vblank_counter,
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.get_scanoutpos = optc1_get_crtc_scanoutpos,
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.get_otg_active_size = optc1_get_otg_active_size,
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.set_early_control = optc1_set_early_control,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.wait_for_state = optc1_wait_for_state,
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.set_blank_color = optc3_program_blank_color,
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.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
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.triplebuffer_lock = optc3_triplebuffer_lock,
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.triplebuffer_unlock = optc2_triplebuffer_unlock,
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.enable_reset_trigger = optc1_enable_reset_trigger,
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.enable_crtc_reset = optc1_enable_crtc_reset,
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.disable_reset_trigger = optc1_disable_reset_trigger,
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.lock = optc3_lock,
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.unlock = optc1_unlock,
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.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
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.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
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.enable_optc_clock = optc1_enable_optc_clock,
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.set_drr = optc32_set_drr,
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.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
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.set_vtotal_min_max = optc3_set_vtotal_min_max,
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.set_static_screen_control = optc1_set_static_screen_control,
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.program_stereo = optc1_program_stereo,
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.is_stereo_left_eye = optc1_is_stereo_left_eye,
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.tg_init = optc3_tg_init,
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.is_tg_enabled = optc1_is_tg_enabled,
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.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
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.clear_optc_underflow = optc1_clear_optc_underflow,
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.setup_global_swap_lock = NULL,
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.get_crc = optc1_get_crc,
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.configure_crc = optc1_configure_crc,
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.set_dsc_config = optc3_set_dsc_config,
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.get_dsc_status = optc2_get_dsc_status,
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.set_dwb_source = NULL,
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.set_odm_bypass = optc32_set_odm_bypass,
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.set_odm_combine = optc32_set_odm_combine,
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.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
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.get_optc_source = optc2_get_optc_source,
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.set_out_mux = optc3_set_out_mux,
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.set_drr_trigger_window = optc3_set_drr_trigger_window,
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.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
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.set_gsl = optc2_set_gsl,
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.set_gsl_source_select = optc2_set_gsl_source_select,
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.set_vtg_params = optc1_set_vtg_params,
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.program_manual_trigger = optc2_program_manual_trigger,
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.setup_manual_trigger = optc2_setup_manual_trigger,
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.get_hw_timing = optc1_get_hw_timing,
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};
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void dcn32_timing_generator_init(struct optc *optc1)
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{
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optc1->base.funcs = &dcn32_tg_funcs;
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optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
|
||
|
|
optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
|
||
|
|
|
||
|
|
optc1->min_h_blank = 32;
|
||
|
|
optc1->min_v_blank = 3;
|
||
|
|
optc1->min_v_blank_interlace = 5;
|
||
|
|
optc1->min_h_sync_width = 4;
|
||
|
|
optc1->min_v_sync_width = 1;
|
||
|
|
}
|
||
|
|
|