289 lines
8.9 KiB
C
289 lines
8.9 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/**
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* This file defines external dependencies of Display Core.
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*/
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#ifndef __DM_SERVICES_H__
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#define __DM_SERVICES_H__
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/* TODO: remove when DC is complete. */
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#include "dm_services_types.h"
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#include "logger_interface.h"
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#include "link_service_types.h"
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#undef DEPRECATED
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struct dmub_srv;
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struct dc_dmub_srv;
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irq_handler_idx dm_register_interrupt(
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struct dc_context *ctx,
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struct dc_interrupt_params *int_params,
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interrupt_handler ih,
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void *handler_args);
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/*
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*
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* GPU registers access
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*
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*/
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uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
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const char *func_name);
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/* enable for debugging new code, this adds 50k to the driver size. */
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/* #define DM_CHECK_ADDR_0 */
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void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
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uint32_t value, const char *func_name);
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#define dm_read_reg(ctx, address) \
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dm_read_reg_func(ctx, address, __func__)
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#define dm_write_reg(ctx, address, value) \
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dm_write_reg_func(ctx, address, value, __func__)
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static inline uint32_t dm_read_index_reg(
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const struct dc_context *ctx,
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enum cgs_ind_reg addr_space,
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uint32_t index)
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{
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return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
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}
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static inline void dm_write_index_reg(
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const struct dc_context *ctx,
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enum cgs_ind_reg addr_space,
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uint32_t index,
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uint32_t value)
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{
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cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
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}
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static inline uint32_t get_reg_field_value_ex(
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uint32_t reg_value,
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uint32_t mask,
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uint8_t shift)
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{
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return (mask & reg_value) >> shift;
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}
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#define get_reg_field_value(reg_value, reg_name, reg_field)\
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get_reg_field_value_ex(\
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(reg_value),\
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reg_name ## __ ## reg_field ## _MASK,\
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reg_name ## __ ## reg_field ## __SHIFT)
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static inline uint32_t set_reg_field_value_ex(
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uint32_t reg_value,
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uint32_t value,
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uint32_t mask,
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uint8_t shift)
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{
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ASSERT(mask != 0);
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return (reg_value & ~mask) | (mask & (value << shift));
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}
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#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
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(reg_value) = set_reg_field_value_ex(\
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(reg_value),\
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(value),\
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reg_name ## __ ## reg_field ## _MASK,\
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reg_name ## __ ## reg_field ## __SHIFT)
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uint32_t generic_reg_set_ex(const struct dc_context *ctx,
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uint32_t addr, uint32_t reg_val, int n,
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uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
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uint32_t generic_reg_update_ex(const struct dc_context *ctx,
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uint32_t addr, int n,
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uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
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struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
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void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
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void reg_sequence_start_gather(const struct dc_context *ctx);
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void reg_sequence_start_execute(const struct dc_context *ctx);
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void reg_sequence_wait_done(const struct dc_context *ctx);
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#define FD(reg_field) reg_field ## __SHIFT, \
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reg_field ## _MASK
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/*
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* return number of poll before condition is met
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* return 0 if condition is not meet after specified time out tries
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*/
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void generic_reg_wait(const struct dc_context *ctx,
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uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
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unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
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const char *func_name, int line);
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unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
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/* These macros need to be used with soc15 registers in order to retrieve
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* the actual offset.
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*/
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#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
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dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
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#define dm_read_reg_soc15(ctx, reg, inst_offset) \
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dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
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#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
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generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
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n, __VA_ARGS__)
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#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
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generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
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n, __VA_ARGS__)
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#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
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get_reg_field_value_ex(\
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(reg_value),\
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block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
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block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
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#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
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(reg_value) = set_reg_field_value_ex(\
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(reg_value),\
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(value),\
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block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
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block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
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/**************************************
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* Power Play (PP) interfaces
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**************************************/
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/* Gets valid clocks levels from pplib
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*
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* input: clk_type - display clk / sclk / mem clk
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*
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* output: array of valid clock levels for given type in ascending order,
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* with invalid levels filtered out
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*
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*/
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bool dm_pp_get_clock_levels_by_type(
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const struct dc_context *ctx,
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels *clk_level_info);
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bool dm_pp_get_clock_levels_by_type_with_latency(
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const struct dc_context *ctx,
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels_with_latency *clk_level_info);
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bool dm_pp_get_clock_levels_by_type_with_voltage(
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const struct dc_context *ctx,
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels_with_voltage *clk_level_info);
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bool dm_pp_notify_wm_clock_changes(
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const struct dc_context *ctx,
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struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
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void dm_pp_get_funcs(struct dc_context *ctx,
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struct pp_smu_funcs *funcs);
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/* DAL calls this function to notify PP about completion of Mode Set.
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* For PP it means that current DCE clocks are those which were returned
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* by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
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*
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* If the clocks are higher than before, then PP does nothing.
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*
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* If the clocks are lower than before, then PP reduces the voltage.
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*
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* \returns true - call is successful
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* false - call failed
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*/
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bool dm_pp_apply_display_requirements(
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const struct dc_context *ctx,
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const struct dm_pp_display_configuration *pp_display_cfg);
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bool dm_pp_apply_power_level_change_request(
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const struct dc_context *ctx,
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struct dm_pp_power_level_change_request *level_change_req);
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bool dm_pp_apply_clock_for_voltage_request(
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const struct dc_context *ctx,
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struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
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bool dm_pp_get_static_clocks(
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const struct dc_context *ctx,
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struct dm_pp_static_clock_info *static_clk_info);
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/****** end of PP interfaces ******/
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struct persistent_data_flag {
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bool save_per_link;
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bool save_per_edid;
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};
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bool dm_query_extended_brightness_caps
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(struct dc_context *ctx, enum dm_acpi_display_type display,
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struct dm_acpi_atif_backlight_caps *pCaps);
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bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
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/*
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*
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* print-out services
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*
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*/
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#define dm_log_to_buffer(buffer, size, fmt, args)\
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vsnprintf(buffer, size, fmt, args)
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static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
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{
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return ktime_get_raw_ns();
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}
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unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
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unsigned long long current_time_stamp,
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unsigned long long last_time_stamp);
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/*
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* performance tracing
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*/
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void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx);
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#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX)
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#define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
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/*
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* Debug and verification hooks
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*/
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void dm_dtn_log_begin(struct dc_context *ctx,
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struct dc_log_buffer_ctx *log_ctx);
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void dm_dtn_log_append_v(struct dc_context *ctx,
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struct dc_log_buffer_ctx *log_ctx,
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const char *msg, ...);
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void dm_dtn_log_end(struct dc_context *ctx,
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struct dc_log_buffer_ctx *log_ctx);
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#endif /* __DM_SERVICES_H__ */
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