111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DSC_H__
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#define __DAL_DSC_H__
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#include "dc_dsc.h"
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#include "dc_hw_types.h"
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#include "dc_types.h"
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/* do not include any other headers
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* or else it might break Edid Utility functionality.
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*/
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/* Input parameters for configuring DSC from the outside of DSC */
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struct dsc_config {
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uint32_t pic_width;
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uint32_t pic_height;
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enum dc_pixel_encoding pixel_encoding;
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enum dc_color_depth color_depth; /* Bits per component */
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bool is_odm;
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struct dc_dsc_config dc_dsc_cfg;
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};
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/* Output parameters for configuring DSC-related part of OPTC */
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struct dsc_optc_config {
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uint32_t slice_width; /* Slice width in pixels */
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uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */
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bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */
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};
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struct dcn_dsc_state {
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uint32_t dsc_clock_en;
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uint32_t dsc_slice_width;
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uint32_t dsc_bits_per_pixel;
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uint32_t dsc_slice_height;
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uint32_t dsc_pic_width;
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uint32_t dsc_pic_height;
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uint32_t dsc_slice_bpg_offset;
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uint32_t dsc_chunk_size;
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uint32_t dsc_fw_en;
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uint32_t dsc_opp_source;
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};
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/* DSC encoder capabilities
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* They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
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*/
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union dsc_enc_slice_caps {
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struct {
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uint8_t NUM_SLICES_1 : 1;
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uint8_t NUM_SLICES_2 : 1;
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uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
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uint8_t NUM_SLICES_4 : 1;
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uint8_t NUM_SLICES_8 : 1;
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} bits;
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uint8_t raw;
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};
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struct dsc_enc_caps {
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uint8_t dsc_version;
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union dsc_enc_slice_caps slice_caps;
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int32_t lb_bit_depth;
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bool is_block_pred_supported;
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union dsc_color_formats color_formats;
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union dsc_color_depth color_depth;
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int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
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int32_t max_slice_width;
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uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
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uint32_t edp_sink_max_bits_per_pixel;
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bool is_dp;
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};
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struct dsc_funcs {
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void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
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void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
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bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
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void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
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struct dsc_optc_config *dsc_optc_cfg);
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bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
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uint8_t *dsc_packed_pps);
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void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
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void (*dsc_disable)(struct display_stream_compressor *dsc);
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void (*dsc_disconnect)(struct display_stream_compressor *dsc);
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};
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#endif
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