292 lines
9.4 KiB
C
292 lines
9.4 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_ASIC_ID_H__
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#define __DAL_ASIC_ID_H__
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/*
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* ASIC internal revision ID
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*/
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/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
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#define SI_TAHITI_P_A0 0x01
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#define SI_TAHITI_P_B0 0x05
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#define SI_TAHITI_P_B1 0x06
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#define SI_PITCAIRN_PM_A0 0x14
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#define SI_PITCAIRN_PM_A1 0x15
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#define SI_CAPEVERDE_M_A0 0x28
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#define SI_CAPEVERDE_M_A1 0x29
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#define SI_OLAND_M_A0 0x3C
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#define SI_HAINAN_V_A0 0x46
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#define SI_UNKNOWN 0xFF
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#define ASIC_REV_IS_TAHITI_P(rev) \
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((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
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#define ASIC_REV_IS_PITCAIRN_PM(rev) \
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((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
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#define ASIC_REV_IS_CAPEVERDE_M(rev) \
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((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
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#define ASIC_REV_IS_OLAND_M(rev) \
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((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
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#define ASIC_REV_IS_HAINAN_V(rev) \
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((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
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/* DCE80 (based on ci_id.h in Perforce) */
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#define CI_BONAIRE_M_A0 0x14
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#define CI_BONAIRE_M_A1 0x15
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#define CI_HAWAII_P_A0 0x28
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#define CI_UNKNOWN 0xFF
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#define ASIC_REV_IS_BONAIRE_M(rev) \
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((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
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#define ASIC_REV_IS_HAWAII_P(rev) \
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(rev >= CI_HAWAII_P_A0)
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/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
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#define KV_SPECTRE_A0 0x01
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/* KV2 with Spooky GFX core, including downgraded from Spectre core,
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* 3-4-1-1 (CU-Pix-Primitive-RB) */
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#define KV_SPOOKY_A0 0x41
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/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
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#define KB_KALINDI_A0 0x81
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/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
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#define KB_KALINDI_A1 0x82
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/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
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#define BV_KALINDI_A2 0x85
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/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
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#define ML_GODAVARI_A0 0xA1
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/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
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#define ML_GODAVARI_A1 0xA2
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#define KV_UNKNOWN 0xFF
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#define ASIC_REV_IS_KALINDI(rev) \
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((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
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#define ASIC_REV_IS_BHAVANI(rev) \
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((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
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#define ASIC_REV_IS_GODAVARI(rev) \
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((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
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/* VI Family */
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/* DCE10 */
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#define VI_TONGA_P_A0 20
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#define VI_TONGA_P_A1 21
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#define VI_FIJI_P_A0 60
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/* DCE112 */
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#define VI_POLARIS10_P_A0 80
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#define VI_POLARIS11_M_A0 90
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#define VI_POLARIS12_V_A0 100
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#define VI_VEGAM_A0 110
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#define VI_UNKNOWN 0xFF
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#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
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(eChipRev < 40))
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#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
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(eChipRev < 80))
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#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
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(eChipRev < VI_POLARIS11_M_A0))
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#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \
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(eChipRev < VI_POLARIS12_V_A0))
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#define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
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(eChipRev < VI_VEGAM_A0))
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#define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
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/* DCE11 */
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#define CZ_CARRIZO_A0 0x01
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#define STONEY_A0 0x61
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#define CZ_UNKNOWN 0xFF
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#define ASIC_REV_IS_STONEY(rev) \
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((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
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/* DCE12 */
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#define AI_UNKNOWN 0xFF
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#define AI_GREENLAND_P_A0 1
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#define AI_GREENLAND_P_A1 2
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#define AI_UNKNOWN 0xFF
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#define AI_VEGA12_P_A0 20
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#define AI_VEGA20_P_A0 40
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#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
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#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
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#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0))
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#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN))
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/* DCN1_0 */
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#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
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#define RAVEN_A0 0x01
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#define RAVEN_B0 0x21
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#define PICASSO_A0 0x41
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/* DCN1_01 */
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#define RAVEN2_A0 0x81
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#define RAVEN1_F0 0xF0
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#define RAVEN_UNKNOWN 0xFF
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#define RENOIR_A0 0x91
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#ifndef ASICREV_IS_RAVEN
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#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
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#endif
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#define PRID_DALI_DE 0xDE
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#define PRID_DALI_DF 0xDF
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#define PRID_DALI_E3 0xE3
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#define PRID_DALI_E4 0xE4
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#define PRID_POLLOCK_94 0x94
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#define PRID_POLLOCK_95 0x95
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#define PRID_POLLOCK_E9 0xE9
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#define PRID_POLLOCK_EA 0xEA
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#define PRID_POLLOCK_EB 0xEB
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#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
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#ifndef ASICREV_IS_RAVEN2
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#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0))
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#endif
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#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
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#define FAMILY_RV 142 /* DCN 1*/
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#define FAMILY_NV 143 /* DCN 2*/
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enum {
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NV_NAVI10_P_A0 = 1,
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NV_NAVI12_P_A0 = 10,
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NV_NAVI14_M_A0 = 20,
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NV_SIENNA_CICHLID_P_A0 = 40,
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NV_DIMGREY_CAVEFISH_P_A0 = 60,
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NV_BEIGE_GOBY_P_A0 = 70,
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NV_UNKNOWN = 0xFF
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};
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#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0)
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#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
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#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
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#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
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#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0))
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#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_BEIGE_GOBY_P_A0))
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#define ASICREV_IS_BEIGE_GOBY_P(eChipRev) ((eChipRev >= NV_BEIGE_GOBY_P_A0) && (eChipRev < NV_UNKNOWN))
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#define GREEN_SARDINE_A0 0xA1
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#ifndef ASICREV_IS_GREEN_SARDINE
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#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
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#endif
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#define DEVICE_ID_NV_13FE 0x13FE // CYAN_SKILLFISH
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#define DEVICE_ID_NV_143F 0x143F
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#define FAMILY_VGH 144
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#define DEVICE_ID_VGH_163F 0x163F
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#define DEVICE_ID_VGH_1435 0x1435
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#define VANGOGH_A0 0x01
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#define VANGOGH_UNKNOWN 0xFF
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#ifndef ASICREV_IS_VANGOGH
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#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
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#endif
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#define FAMILY_YELLOW_CARP 146
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#define YELLOW_CARP_A0 0x01
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#define YELLOW_CARP_B0 0x20
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#define YELLOW_CARP_UNKNOWN 0xFF
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#ifndef ASICREV_IS_YELLOW_CARP
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#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
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#endif
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#define AMDGPU_FAMILY_GC_10_3_6 149
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#define GC_10_3_6_A0 0x01
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#define GC_10_3_6_UNKNOWN 0xFF
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#define ASICREV_IS_GC_10_3_6(eChipRev) ((eChipRev >= GC_10_3_6_A0) && (eChipRev < GC_10_3_6_UNKNOWN))
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#define AMDGPU_FAMILY_GC_10_3_7 151
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#define GC_10_3_7_A0 0x01
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#define GC_10_3_7_UNKNOWN 0xFF
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#define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN))
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#define AMDGPU_FAMILY_GC_11_0_0 145
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#define AMDGPU_FAMILY_GC_11_0_1 148
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#define GC_11_0_0_A0 0x1
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#define GC_11_0_2_A0 0x10
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#define GC_11_0_3_A0 0x20
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#define GC_11_UNKNOWN 0xFF
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#define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0)
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#define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < GC_11_0_3_A0)
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#define ASICREV_IS_GC_11_0_3(eChipRev) (eChipRev >= GC_11_0_3_A0 && eChipRev < GC_11_UNKNOWN)
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/*
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* ASIC chip ID
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*/
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/* DCE60 */
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#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
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#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
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#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
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#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
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#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
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#define DEVICE_ID_SI_OLAND_M_6600 0x6600
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#define DEVICE_ID_SI_OLAND_M_6608 0x6608
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#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
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/* DCE80 */
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#define DEVICE_ID_KALINDI_9834 0x9834
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#define DEVICE_ID_TEMASH_9839 0x9839
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#define DEVICE_ID_TEMASH_983D 0x983D
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/* RENOIR */
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#define DEVICE_ID_RENOIR_1636 0x1636
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/* Asic Family IDs for different asic family. */
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#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */
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#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
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#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
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#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
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#define FAMILY_CZ 135 /* Carrizo */
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#define FAMILY_AI 141
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#define FAMILY_UNKNOWN 0xFF
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#endif /* __DAL_ASIC_ID_H__ */
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