312 lines
8.1 KiB
C
312 lines
8.1 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _SMU8_HWMGR_H_
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#define _SMU8_HWMGR_H_
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#include "cgs_common.h"
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#include "ppatomctrl.h"
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#define SMU8_NUM_NBPSTATES 4
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#define SMU8_NUM_NBPMEMORYCLOCK 2
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#define MAX_DISPLAY_CLOCK_LEVEL 8
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#define SMU8_MAX_HARDWARE_POWERLEVELS 8
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#define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
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#define SMU8_MIN_DEEP_SLEEP_SCLK 800
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/* Carrizo device IDs */
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#define DEVICE_ID_CZ_9870 0x9870
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#define DEVICE_ID_CZ_9874 0x9874
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#define DEVICE_ID_CZ_9875 0x9875
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#define DEVICE_ID_CZ_9876 0x9876
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#define DEVICE_ID_CZ_9877 0x9877
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struct smu8_dpm_entry {
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uint32_t soft_min_clk;
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uint32_t hard_min_clk;
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uint32_t soft_max_clk;
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uint32_t hard_max_clk;
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};
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struct smu8_sys_info {
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uint32_t bootup_uma_clock;
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uint32_t bootup_engine_clock;
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uint32_t dentist_vco_freq;
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uint32_t nb_dpm_enable;
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uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
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uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
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uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES];
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uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
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uint16_t bootup_nb_voltage_index;
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uint8_t htc_tmp_lmt;
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uint8_t htc_hyst_lmt;
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uint32_t system_config;
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uint32_t uma_channel_number;
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};
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#define MAX_DISPLAYPHY_IDS 0x8
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#define DISPLAYPHY_LANEMASK 0xF
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#define UNKNOWN_TRANSMITTER_PHY_ID (-1)
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#define DISPLAYPHY_PHYID_SHIFT 24
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#define DISPLAYPHY_LANESELECT_SHIFT 16
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#define DISPLAYPHY_RX_SELECT 0x1
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#define DISPLAYPHY_TX_SELECT 0x2
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#define DISPLAYPHY_CORE_SELECT 0x4
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#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
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(((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \
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((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \
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((rx) ? DISPLAYPHY_RX_SELECT : 0) | \
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((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
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((core) ? DISPLAYPHY_CORE_SELECT : 0))
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struct smu8_display_phy_info_entry {
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uint8_t phy_present;
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uint8_t active_lane_mapping;
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uint8_t display_config_type;
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uint8_t active_number_of_lanes;
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};
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#define SMU8_MAX_DISPLAYPHY_IDS 10
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struct smu8_display_phy_info {
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bool display_phy_access_initialized;
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struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS];
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};
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struct smu8_power_level {
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uint32_t engineClock;
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uint8_t vddcIndex;
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uint8_t dsDividerIndex;
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uint8_t ssDividerIndex;
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uint8_t allowGnbSlow;
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uint8_t forceNBPstate;
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uint8_t display_wm;
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uint8_t vce_wm;
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uint8_t numSIMDToPowerDown;
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uint8_t hysteresis_up;
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uint8_t rsv[3];
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};
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struct smu8_uvd_clocks {
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uint32_t vclk;
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uint32_t dclk;
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uint32_t vclk_low_divider;
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uint32_t vclk_high_divider;
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uint32_t dclk_low_divider;
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uint32_t dclk_high_divider;
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};
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enum smu8_pstate_previous_action {
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DO_NOTHING = 1,
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FORCE_HIGH,
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CANCEL_FORCE_HIGH
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};
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struct pp_disable_nb_ps_flags {
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union {
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struct {
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uint32_t entry : 1;
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uint32_t display : 1;
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uint32_t driver: 1;
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uint32_t vce : 1;
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uint32_t uvd : 1;
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uint32_t acp : 1;
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uint32_t reserved: 26;
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} bits;
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uint32_t u32All;
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};
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};
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struct smu8_power_state {
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unsigned int magic;
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uint32_t level;
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struct smu8_uvd_clocks uvd_clocks;
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uint32_t evclk;
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uint32_t ecclk;
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uint32_t samclk;
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uint32_t acpclk;
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bool need_dfs_bypass;
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uint32_t nbps_flags;
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uint32_t bapm_flags;
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uint8_t dpm_0_pg_nb_ps_low;
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uint8_t dpm_0_pg_nb_ps_high;
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uint8_t dpm_x_nb_ps_low;
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uint8_t dpm_x_nb_ps_high;
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enum smu8_pstate_previous_action action;
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struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS];
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struct pp_disable_nb_ps_flags disable_nb_ps_flag;
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};
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#define DPMFlags_SCLK_Enabled 0x00000001
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#define DPMFlags_UVD_Enabled 0x00000002
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#define DPMFlags_VCE_Enabled 0x00000004
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#define DPMFlags_ACP_Enabled 0x00000008
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#define DPMFlags_ForceHighestValid 0x40000000
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#define DPMFlags_Debug 0x80000000
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#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */
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#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */
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#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */
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struct cc6_settings {
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bool cc6_setting_changed;
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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};
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struct smu8_hwmgr {
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uint32_t dpm_interval;
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uint32_t voltage_drop_threshold;
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uint32_t voting_rights_clients;
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uint32_t disable_driver_thermal_policy;
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uint32_t static_screen_threshold;
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uint32_t gfx_power_gating_threshold;
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uint32_t activity_hysteresis;
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uint32_t bootup_sclk_divider;
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uint32_t gfx_ramp_step;
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uint32_t gfx_ramp_delay; /* in micro-seconds */
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uint32_t thermal_auto_throttling_treshold;
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struct smu8_sys_info sys_info;
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struct smu8_power_level boot_power_level;
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struct smu8_power_state *smu8_current_ps;
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struct smu8_power_state *smu8_requested_ps;
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uint32_t mgcg_cgtt_local0;
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uint32_t mgcg_cgtt_local1;
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uint32_t tdr_clock; /* in 10khz unit */
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uint32_t ddi_power_gating_disabled;
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uint32_t disable_gfx_power_gating_in_uvd;
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uint32_t disable_nb_ps3_in_battery;
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uint32_t lock_nb_ps_in_uvd_play_back;
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struct smu8_display_phy_info display_phy_info;
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uint32_t vce_slow_sclk_threshold; /* default 200mhz */
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uint32_t dce_slow_sclk_threshold; /* default 300mhz */
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uint32_t min_sclk_did; /* minimum sclk divider */
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bool disp_clk_bypass;
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bool disp_clk_bypass_pending;
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uint32_t bapm_enabled;
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uint32_t clock_slow_down_freq;
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uint32_t skip_clock_slow_down;
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uint32_t enable_nb_ps_policy;
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uint32_t voltage_drop_in_dce_power_gating;
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uint32_t uvd_dpm_interval;
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uint32_t override_dynamic_mgpg;
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uint32_t lclk_deep_enabled;
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uint32_t uvd_performance;
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bool video_start;
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bool battery_state;
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uint32_t lowest_valid;
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uint32_t highest_valid;
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uint32_t high_voltage_threshold;
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uint32_t is_nb_dpm_enabled;
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struct cc6_settings cc6_settings;
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uint32_t is_voltage_island_enabled;
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bool pgacpinit;
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uint8_t disp_config;
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/* PowerTune */
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uint32_t power_containment_features;
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bool cac_enabled;
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bool disable_uvd_power_tune_feature;
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bool enable_ba_pm_feature;
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bool enable_tdc_limit_feature;
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uint32_t sram_end;
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uint32_t dpm_table_start;
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uint32_t soft_regs_start;
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uint8_t uvd_level_count;
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uint8_t vce_level_count;
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uint8_t acp_level_count;
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uint8_t samu_level_count;
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uint32_t fps_high_threshold;
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uint32_t fps_low_threshold;
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uint32_t dpm_flags;
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struct smu8_dpm_entry sclk_dpm;
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struct smu8_dpm_entry uvd_dpm;
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struct smu8_dpm_entry vce_dpm;
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struct smu8_dpm_entry acp_dpm;
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uint8_t uvd_boot_level;
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uint8_t vce_boot_level;
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uint8_t acp_boot_level;
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uint8_t samu_boot_level;
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uint8_t uvd_interval;
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uint8_t vce_interval;
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uint8_t acp_interval;
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uint8_t samu_interval;
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uint8_t graphics_interval;
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uint8_t graphics_therm_throttle_enable;
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uint8_t graphics_voltage_change_enable;
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uint8_t graphics_clk_slow_enable;
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uint8_t graphics_clk_slow_divider;
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uint32_t display_cac;
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uint32_t low_sclk_interrupt_threshold;
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uint32_t dram_log_addr_h;
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uint32_t dram_log_addr_l;
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uint32_t dram_log_phy_addr_h;
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uint32_t dram_log_phy_addr_l;
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uint32_t dram_log_buff_size;
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bool uvd_power_gated;
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bool vce_power_gated;
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bool samu_power_gated;
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bool acp_power_gated;
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bool acp_power_up_no_dsp;
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uint32_t active_process_mask;
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uint32_t max_sclk_level;
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uint32_t num_of_clk_entries;
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};
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#endif /* _SMU8_HWMGR_H_ */
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