242 lines
9.6 KiB
C
242 lines
9.6 KiB
C
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _SMU_HELPER_H_
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#define _SMU_HELPER_H_
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struct pp_atomctrl_voltage_table;
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struct pp_hwmgr;
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struct phm_ppt_v1_voltage_lookup_table;
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struct Watermarks_t;
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struct pp_wm_sets_with_clock_ranges_soc15;
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uint8_t convert_to_vid(uint16_t vddc);
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uint16_t convert_to_vddc(uint8_t vid);
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struct watermark_row_generic_t {
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uint16_t MinClock;
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uint16_t MaxClock;
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uint16_t MinUclk;
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uint16_t MaxUclk;
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uint8_t WmSetting;
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uint8_t Padding[3];
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};
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struct watermarks {
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struct watermark_row_generic_t WatermarkRow[2][4];
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uint32_t padding[7];
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};
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int phm_copy_clock_limits_array(
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struct pp_hwmgr *hwmgr,
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uint32_t **pptable_info_array,
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const uint32_t *pptable_array,
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uint32_t power_saving_clock_count);
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int phm_copy_overdrive_settings_limits_array(
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struct pp_hwmgr *hwmgr,
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uint32_t **pptable_info_array,
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const uint32_t *pptable_array,
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uint32_t od_setting_count);
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extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
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uint32_t index,
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uint32_t value, uint32_t mask);
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extern int phm_wait_for_indirect_register_unequal(
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struct pp_hwmgr *hwmgr,
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uint32_t indirect_port, uint32_t index,
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uint32_t value, uint32_t mask);
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extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
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extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
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extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
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extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
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extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
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extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
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extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
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extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
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extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
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extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
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extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
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extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
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uint32_t voltage);
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extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
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extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
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extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
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extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
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uint16_t virtual_voltage_id, int32_t *sclk);
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extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
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extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
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extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
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extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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uint32_t sclk, uint16_t id, uint16_t *voltage);
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extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);
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extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
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uint32_t value, uint32_t mask);
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extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
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uint32_t indirect_port,
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uint32_t index,
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uint32_t value,
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uint32_t mask);
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int phm_irq_process(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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/*
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* Helper function to make sysfs_emit_at() happy. Align buf to
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* the current page boundary and record the offset.
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*/
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static inline void phm_get_sysfs_buf(char **buf, int *offset)
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{
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if (!*buf || !offset)
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return;
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*offset = offset_in_page(*buf);
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*buf -= *offset;
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}
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int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr);
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void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
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uint8_t *frev, uint8_t *crev);
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int smu_get_voltage_dependency_table_ppt_v1(
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const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
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int smu_set_watermarks_for_clocks_ranges(void *wt_table,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
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#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
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#define PHM_SET_FIELD(origval, reg, field, fieldval) \
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(((origval) & ~PHM_FIELD_MASK(reg, field)) | \
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(PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
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#define PHM_GET_FIELD(value, reg, field) \
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(((value) & PHM_FIELD_MASK(reg, field)) >> \
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PHM_FIELD_SHIFT(reg, field))
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/* Operations on named fields. */
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#define PHM_READ_FIELD(device, reg, field) \
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PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
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#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
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PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field)
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#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
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PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field)
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#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
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cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
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cgs_read_register(device, mm##reg), reg, field, fieldval))
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#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
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cgs_write_ind_register(device, port, ix##reg, \
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PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field, fieldval))
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#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
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cgs_write_ind_register(device, port, ix##reg, \
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PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field, fieldval))
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#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
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phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
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#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
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PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
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#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
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PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
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<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
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#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
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phm_wait_for_indirect_register_unequal(hwmgr, \
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mm##port##_INDEX, index, value, mask)
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#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
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PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
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#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
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PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
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(fieldval) << PHM_FIELD_SHIFT(reg, field), \
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PHM_FIELD_MASK(reg, field) )
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#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
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port, index, value, mask) \
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phm_wait_for_indirect_register_unequal(hwmgr, \
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mm##port##_INDEX_11, index, value, mask)
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#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
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PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
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#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
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PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
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(fieldval) << PHM_FIELD_SHIFT(reg, field), \
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PHM_FIELD_MASK(reg, field))
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#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
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port, index, value, mask) \
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phm_wait_on_indirect_register(hwmgr, \
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mm##port##_INDEX_11, index, value, mask)
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#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
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PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
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#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
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PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
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(fieldval) << PHM_FIELD_SHIFT(reg, field), \
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PHM_FIELD_MASK(reg, field))
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#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
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index, value, mask) \
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phm_wait_for_register_unequal(hwmgr, \
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index, value, mask)
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#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
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PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
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mm##reg, value, mask)
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#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
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PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
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(fieldval) << PHM_FIELD_SHIFT(reg, field), \
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PHM_FIELD_MASK(reg, field))
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#endif /* _SMU_HELPER_H_ */
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