459 lines
14 KiB
C
459 lines
14 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _VEGA12_HWMGR_H_
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#define _VEGA12_HWMGR_H_
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#include "hwmgr.h"
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#include "vega12/smu9_driver_if.h"
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#include "ppatomfwctrl.h"
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#define VEGA12_MAX_HARDWARE_POWERLEVELS 2
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#define WaterMarksExist 1
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#define WaterMarksLoaded 2
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#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 16
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#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8
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#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8
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#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4
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enum
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{
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GNLD_DPM_PREFETCHER = 0,
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GNLD_DPM_GFXCLK,
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GNLD_DPM_UCLK,
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GNLD_DPM_SOCCLK,
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GNLD_DPM_UVD,
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GNLD_DPM_VCE,
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GNLD_ULV,
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GNLD_DPM_MP0CLK,
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GNLD_DPM_LINK,
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GNLD_DPM_DCEFCLK,
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GNLD_DS_GFXCLK,
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GNLD_DS_SOCCLK,
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GNLD_DS_LCLK,
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GNLD_PPT,
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GNLD_TDC,
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GNLD_THERMAL,
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GNLD_GFX_PER_CU_CG,
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GNLD_RM,
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GNLD_DS_DCEFCLK,
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GNLD_ACDC,
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GNLD_VR0HOT,
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GNLD_VR1HOT,
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GNLD_FW_CTF,
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GNLD_LED_DISPLAY,
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GNLD_FAN_CONTROL,
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GNLD_DIDT,
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GNLD_GFXOFF,
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GNLD_CG,
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GNLD_ACG,
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GNLD_FEATURES_MAX
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};
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#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1)
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#define SMC_DPM_FEATURES 0x30F
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struct smu_features {
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bool supported;
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bool enabled;
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bool allowed;
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uint32_t smu_feature_id;
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uint64_t smu_feature_bitmap;
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};
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struct vega12_dpm_level {
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bool enabled;
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uint32_t value;
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uint32_t param1;
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};
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#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define MAX_REGULAR_DPM_NUMBER 16
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#define MAX_PCIE_CONF 2
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#define VEGA12_MINIMUM_ENGINE_CLOCK 2500
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struct vega12_dpm_state {
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uint32_t soft_min_level;
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uint32_t soft_max_level;
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uint32_t hard_min_level;
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uint32_t hard_max_level;
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};
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struct vega12_single_dpm_table {
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uint32_t count;
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struct vega12_dpm_state dpm_state;
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struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_odn_dpm_control {
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uint32_t count;
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uint32_t entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_pcie_table {
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uint16_t count;
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uint8_t pcie_gen[MAX_PCIE_CONF];
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uint8_t pcie_lane[MAX_PCIE_CONF];
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uint32_t lclk[MAX_PCIE_CONF];
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};
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struct vega12_dpm_table {
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struct vega12_single_dpm_table soc_table;
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struct vega12_single_dpm_table gfx_table;
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struct vega12_single_dpm_table mem_table;
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struct vega12_single_dpm_table eclk_table;
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struct vega12_single_dpm_table vclk_table;
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struct vega12_single_dpm_table dclk_table;
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struct vega12_single_dpm_table dcef_table;
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struct vega12_single_dpm_table pixel_table;
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struct vega12_single_dpm_table display_table;
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struct vega12_single_dpm_table phy_table;
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struct vega12_pcie_table pcie_table;
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};
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#define VEGA12_MAX_LEAKAGE_COUNT 8
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struct vega12_leakage_voltage {
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uint16_t count;
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uint16_t leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
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uint16_t actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
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};
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struct vega12_display_timing {
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uint32_t min_clock_in_sr;
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uint32_t num_existing_displays;
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};
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struct vega12_dpmlevel_enable_mask {
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uint32_t uvd_dpm_enable_mask;
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uint32_t vce_dpm_enable_mask;
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uint32_t samu_dpm_enable_mask;
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uint32_t sclk_dpm_enable_mask;
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uint32_t mclk_dpm_enable_mask;
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};
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struct vega12_vbios_boot_state {
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bool bsoc_vddc_lock;
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uint8_t uc_cooling_id;
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uint16_t vddc;
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uint16_t vddci;
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uint16_t mvddc;
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uint16_t vdd_gfx;
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uint32_t gfx_clock;
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uint32_t mem_clock;
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uint32_t soc_clock;
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uint32_t dcef_clock;
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uint32_t eclock;
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uint32_t dclock;
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uint32_t vclock;
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
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struct vega12_smc_state_table {
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uint32_t soc_boot_level;
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uint32_t gfx_boot_level;
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uint32_t dcef_boot_level;
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uint32_t mem_boot_level;
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uint32_t uvd_boot_level;
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uint32_t vce_boot_level;
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uint32_t gfx_max_level;
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uint32_t mem_max_level;
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uint8_t vr_hot_gpio;
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uint8_t ac_dc_gpio;
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uint8_t therm_out_gpio;
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uint8_t therm_out_polarity;
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uint8_t therm_out_mode;
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PPTable_t pp_table;
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Watermarks_t water_marks_table;
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AvfsDebugTable_t avfs_debug_table;
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AvfsFuseOverride_t avfs_fuse_override_table;
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SmuMetrics_t smu_metrics;
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DriverSmuConfig_t driver_smu_config;
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DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
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OverDriveTable_t overdrive_table;
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};
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struct vega12_mclk_latency_entries {
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uint32_t frequency;
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uint32_t latency;
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};
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struct vega12_mclk_latency_table {
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uint32_t count;
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struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_registry_data {
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uint64_t disallowed_features;
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uint8_t ac_dc_switch_gpio_support;
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uint8_t acg_loop_support;
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uint8_t clock_stretcher_support;
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uint8_t db_ramping_support;
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uint8_t didt_mode;
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uint8_t didt_support;
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uint8_t edc_didt_support;
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uint8_t force_dpm_high;
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uint8_t fuzzy_fan_control_support;
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uint8_t mclk_dpm_key_disabled;
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uint8_t od_state_in_dc_support;
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uint8_t pcie_lane_override;
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uint8_t pcie_speed_override;
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uint32_t pcie_clock_override;
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uint8_t pcie_dpm_key_disabled;
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uint8_t dcefclk_dpm_key_disabled;
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uint8_t prefetcher_dpm_key_disabled;
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uint8_t quick_transition_support;
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uint8_t regulator_hot_gpio_support;
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uint8_t master_deep_sleep_support;
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uint8_t gfx_clk_deep_sleep_support;
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uint8_t sclk_deep_sleep_support;
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uint8_t lclk_deep_sleep_support;
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uint8_t dce_fclk_deep_sleep_support;
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uint8_t sclk_dpm_key_disabled;
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uint8_t sclk_throttle_low_notification;
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uint8_t skip_baco_hardware;
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uint8_t socclk_dpm_key_disabled;
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uint8_t sq_ramping_support;
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uint8_t tcp_ramping_support;
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uint8_t td_ramping_support;
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uint8_t dbr_ramping_support;
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uint8_t gc_didt_support;
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uint8_t psm_didt_support;
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uint8_t thermal_support;
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uint8_t fw_ctf_enabled;
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uint8_t led_dpm_enabled;
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uint8_t fan_control_support;
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uint8_t ulv_support;
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uint8_t odn_feature_enable;
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uint8_t disable_water_mark;
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uint8_t disable_workload_policy;
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uint32_t force_workload_policy_mask;
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uint8_t disable_3d_fs_detection;
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uint8_t disable_pp_tuning;
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uint8_t disable_xlpp_tuning;
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uint32_t perf_ui_tuning_profile_turbo;
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uint32_t perf_ui_tuning_profile_powerSave;
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uint32_t perf_ui_tuning_profile_xl;
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uint16_t zrpm_stop_temp;
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uint16_t zrpm_start_temp;
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uint32_t stable_pstate_sclk_dpm_percentage;
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uint8_t fps_support;
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uint8_t vr0hot;
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uint8_t vr1hot;
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uint8_t disable_auto_wattman;
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uint32_t auto_wattman_debug;
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uint32_t auto_wattman_sample_period;
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uint8_t auto_wattman_threshold;
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uint8_t log_avfs_param;
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uint8_t enable_enginess;
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uint8_t custom_fan_support;
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uint8_t disable_pcc_limit_control;
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};
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struct vega12_odn_clock_voltage_dependency_table {
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uint32_t count;
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struct phm_ppt_v1_clock_voltage_dependency_record
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entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_odn_dpm_table {
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struct vega12_odn_dpm_control control_gfxclk_state;
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struct vega12_odn_dpm_control control_memclk_state;
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struct phm_odn_clock_levels odn_core_clock_dpm_levels;
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struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
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struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
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struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
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struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_socclk;
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uint32_t odn_mclk_min_limit;
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};
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struct vega12_odn_fan_table {
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uint32_t target_fan_speed;
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uint32_t target_temperature;
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uint32_t min_performance_clock;
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uint32_t min_fan_limit;
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bool force_fan_pwm;
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};
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struct vega12_clock_range {
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uint32_t ACMax;
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uint32_t ACMin;
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uint32_t DCMax;
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};
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struct vega12_hwmgr {
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struct vega12_dpm_table dpm_table;
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struct vega12_dpm_table golden_dpm_table;
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struct vega12_registry_data registry_data;
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struct vega12_vbios_boot_state vbios_boot_state;
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struct vega12_mclk_latency_table mclk_latency_table;
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struct vega12_leakage_voltage vddc_leakage;
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uint32_t vddc_control;
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struct pp_atomfwctrl_voltage_table vddc_voltage_table;
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uint32_t mvdd_control;
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struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
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uint32_t vddci_control;
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struct pp_atomfwctrl_voltage_table vddci_voltage_table;
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uint32_t active_auto_throttle_sources;
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uint32_t water_marks_bitmap;
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struct vega12_odn_dpm_table odn_dpm_table;
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struct vega12_odn_fan_table odn_fan_table;
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/* ---- General data ---- */
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uint8_t need_update_dpm_table;
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bool cac_enabled;
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bool battery_state;
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bool is_tlu_enabled;
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bool avfs_exist;
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uint32_t low_sclk_interrupt_threshold;
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uint32_t total_active_cus;
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struct vega12_display_timing display_timing;
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||
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/* ---- Vega12 Dyn Register Settings ---- */
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||
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uint32_t debug_settings;
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uint32_t lowest_uclk_reserved_for_ulv;
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||
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uint32_t gfxclk_average_alpha;
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||
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uint32_t socclk_average_alpha;
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||
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uint32_t uclk_average_alpha;
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||
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uint32_t gfx_activity_average_alpha;
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||
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uint32_t display_voltage_mode;
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||
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uint32_t dcef_clk_quad_eqn_a;
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||
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uint32_t dcef_clk_quad_eqn_b;
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||
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uint32_t dcef_clk_quad_eqn_c;
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||
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uint32_t disp_clk_quad_eqn_a;
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||
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uint32_t disp_clk_quad_eqn_b;
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||
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uint32_t disp_clk_quad_eqn_c;
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||
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uint32_t pixel_clk_quad_eqn_a;
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||
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uint32_t pixel_clk_quad_eqn_b;
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||
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uint32_t pixel_clk_quad_eqn_c;
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||
|
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uint32_t phy_clk_quad_eqn_a;
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||
|
|
uint32_t phy_clk_quad_eqn_b;
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||
|
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uint32_t phy_clk_quad_eqn_c;
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||
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|
||
|
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/* ---- Thermal Temperature Setting ---- */
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||
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struct vega12_dpmlevel_enable_mask dpm_level_enable_mask;
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||
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|
||
|
|
/* ---- Power Gating States ---- */
|
||
|
|
bool uvd_power_gated;
|
||
|
|
bool vce_power_gated;
|
||
|
|
bool samu_power_gated;
|
||
|
|
bool need_long_memory_training;
|
||
|
|
|
||
|
|
/* Internal settings to apply the application power optimization parameters */
|
||
|
|
bool apply_optimized_settings;
|
||
|
|
uint32_t disable_dpm_mask;
|
||
|
|
|
||
|
|
/* ---- Overdrive next setting ---- */
|
||
|
|
uint32_t apply_overdrive_next_settings_mask;
|
||
|
|
|
||
|
|
/* ---- Workload Mask ---- */
|
||
|
|
uint32_t workload_mask;
|
||
|
|
|
||
|
|
/* ---- SMU9 ---- */
|
||
|
|
uint32_t smu_version;
|
||
|
|
struct smu_features smu_features[GNLD_FEATURES_MAX];
|
||
|
|
struct vega12_smc_state_table smc_state_table;
|
||
|
|
|
||
|
|
struct vega12_clock_range clk_range[PPCLK_COUNT];
|
||
|
|
|
||
|
|
/* ---- Gfxoff ---- */
|
||
|
|
bool gfxoff_controlled_by_driver;
|
||
|
|
|
||
|
|
unsigned long metrics_time;
|
||
|
|
SmuMetrics_t metrics_table;
|
||
|
|
struct gpu_metrics_v1_0 gpu_metrics_table;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_NEAR_TDP_DEC 10
|
||
|
|
#define VEGA12_DPM2_ABOVE_SAFE_INC 5
|
||
|
|
#define VEGA12_DPM2_BELOW_SAFE_INC 20
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_LTA_WINDOW_SIZE 7
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_LTS_TRUNCATE 0
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT 80
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_MAXPS_PERCENT_M 90
|
||
|
|
#define VEGA12_DPM2_MAXPS_PERCENT_H 90
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN 50
|
||
|
|
|
||
|
|
#define VEGA12_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
|
||
|
|
#define VEGA12_DPM2_SQ_RAMP_MIN_POWER 0x12
|
||
|
|
#define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
|
||
|
|
#define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E
|
||
|
|
#define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF
|
||
|
|
|
||
|
|
#define VEGA12_VOLTAGE_CONTROL_NONE 0x0
|
||
|
|
#define VEGA12_VOLTAGE_CONTROL_BY_GPIO 0x1
|
||
|
|
#define VEGA12_VOLTAGE_CONTROL_BY_SVID2 0x2
|
||
|
|
#define VEGA12_VOLTAGE_CONTROL_MERGED 0x3
|
||
|
|
/* To convert to Q8.8 format for firmware */
|
||
|
|
#define VEGA12_Q88_FORMAT_CONVERSION_UNIT 256
|
||
|
|
|
||
|
|
#define VEGA12_UNUSED_GPIO_PIN 0x7F
|
||
|
|
|
||
|
|
#define VEGA12_THERM_OUT_MODE_DISABLE 0x0
|
||
|
|
#define VEGA12_THERM_OUT_MODE_THERM_ONLY 0x1
|
||
|
|
#define VEGA12_THERM_OUT_MODE_THERM_VRHOT 0x2
|
||
|
|
|
||
|
|
#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||
|
|
#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff
|
||
|
|
|
||
|
|
#define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||
|
|
#define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||
|
|
#define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||
|
|
#define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||
|
|
#define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff
|
||
|
|
#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||
|
|
#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff
|
||
|
|
|
||
|
|
#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL 0x3
|
||
|
|
#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL 0x3
|
||
|
|
#define VEGA12_UMD_PSTATE_MCLK_LEVEL 0x2
|
||
|
|
#define VEGA12_UMD_PSTATE_UVDCLK_LEVEL 0x3
|
||
|
|
#define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL 0x3
|
||
|
|
|
||
|
|
int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
|
||
|
|
|
||
|
|
#endif /* _VEGA12_HWMGR_H_ */
|