345 lines
8.8 KiB
C
345 lines
8.8 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*
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*/
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#include "gem/i915_gem_internal.h"
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_dsb.h"
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struct i915_vma;
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enum dsb_id {
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INVALID_DSB = -1,
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DSB1,
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DSB2,
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DSB3,
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MAX_DSB_PER_PIPE
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};
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struct intel_dsb {
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enum dsb_id id;
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u32 *cmd_buf;
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struct i915_vma *vma;
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struct intel_crtc *crtc;
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/*
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* maximum number of dwords the buffer will hold.
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*/
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unsigned int size;
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/*
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* free_pos will point the first free dword and
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* help in calculating tail of command buffer.
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*/
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unsigned int free_pos;
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/*
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* ins_start_offset will help to store start dword of the dsb
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* instuction and help in identifying the batch of auto-increment
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* register.
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*/
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unsigned int ins_start_offset;
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};
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/**
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* DOC: DSB
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*
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* A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
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* which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
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* engine that can be programmed to download the DSB from memory.
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* It allows driver to batch submit display HW programming. This helps to
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* reduce loading time and CPU activity, thereby making the context switch
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* faster. DSB Support added from Gen12 Intel graphics based platform.
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*
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* DSB's can access only the pipe, plane, and transcoder Data Island Packet
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* registers.
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*
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* DSB HW can support only register writes (both indexed and direct MMIO
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* writes). There are no registers reads possible with DSB HW engine.
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*/
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/* DSB opcodes. */
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#define DSB_OPCODE_SHIFT 24
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#define DSB_OPCODE_NOOP 0x0
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#define DSB_OPCODE_MMIO_WRITE 0x1
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#define DSB_OPCODE_WAIT_USEC 0x2
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#define DSB_OPCODE_WAIT_LINES 0x3
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#define DSB_OPCODE_WAIT_VBLANKS 0x4
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#define DSB_OPCODE_WAIT_DSL_IN 0x5
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#define DSB_OPCODE_WAIT_DSL_OUT 0x6
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#define DSB_OPCODE_INTERRUPT 0x7
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#define DSB_OPCODE_INDEXED_WRITE 0x9
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#define DSB_OPCODE_POLL 0xA
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#define DSB_BYTE_EN 0xF
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#define DSB_BYTE_EN_SHIFT 20
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#define DSB_REG_VALUE_MASK 0xfffff
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static bool assert_dsb_has_room(struct intel_dsb *dsb)
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{
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struct intel_crtc *crtc = dsb->crtc;
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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/* each instruction is 2 dwords */
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return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2,
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"DSB buffer overflow\n");
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}
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static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
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enum dsb_id id)
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{
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return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
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}
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static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
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{
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u32 *buf = dsb->cmd_buf;
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if (!assert_dsb_has_room(dsb))
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return;
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/* Every instruction should be 8 byte aligned. */
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dsb->free_pos = ALIGN(dsb->free_pos, 2);
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dsb->ins_start_offset = dsb->free_pos;
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buf[dsb->free_pos++] = ldw;
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buf[dsb->free_pos++] = udw;
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}
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static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
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u32 opcode, i915_reg_t reg)
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{
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const u32 *buf = dsb->cmd_buf;
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u32 prev_opcode, prev_reg;
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prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT;
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prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
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return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
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}
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static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg)
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{
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return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg);
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}
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static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
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{
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return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg);
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}
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/**
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* intel_dsb_reg_write() - Emit register wriite to the DSB context
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* @dsb: DSB context
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* @reg: register address.
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* @val: value.
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*
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* This function is used for writing register-value pair in command
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* buffer of DSB.
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*/
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void intel_dsb_reg_write(struct intel_dsb *dsb,
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i915_reg_t reg, u32 val)
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{
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/*
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* For example the buffer will look like below for 3 dwords for auto
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* increment register:
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* +--------------------------------------------------------+
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* | size = 3 | offset &| value1 | value2 | value3 | zero |
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* | | opcode | | | | |
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* +--------------------------------------------------------+
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* + + + + + + +
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* 0 4 8 12 16 20 24
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* Byte
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*
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* As every instruction is 8 byte aligned the index of dsb instruction
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* will start always from even number while dealing with u32 array. If
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* we are writing odd no of dwords, Zeros will be added in the end for
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* padding.
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*/
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if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) &&
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!intel_dsb_prev_ins_is_indexed_write(dsb, reg)) {
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intel_dsb_emit(dsb, val,
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(DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
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(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
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i915_mmio_reg_offset(reg));
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} else {
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u32 *buf = dsb->cmd_buf;
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if (!assert_dsb_has_room(dsb))
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return;
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/* convert to indexed write? */
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if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) {
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u32 prev_val = buf[dsb->ins_start_offset + 0];
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buf[dsb->ins_start_offset + 0] = 1; /* count */
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buf[dsb->ins_start_offset + 1] =
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(DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) |
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i915_mmio_reg_offset(reg);
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buf[dsb->ins_start_offset + 2] = prev_val;
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dsb->free_pos++;
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}
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buf[dsb->free_pos++] = val;
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/* Update the count */
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buf[dsb->ins_start_offset]++;
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/* if number of data words is odd, then the last dword should be 0.*/
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if (dsb->free_pos & 0x1)
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buf[dsb->free_pos] = 0;
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}
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}
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static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
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{
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u32 aligned_tail, tail;
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tail = dsb->free_pos * 4;
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aligned_tail = ALIGN(tail, CACHELINE_BYTES);
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if (aligned_tail > tail)
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memset(&dsb->cmd_buf[dsb->free_pos], 0,
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aligned_tail - tail);
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dsb->free_pos = aligned_tail / 4;
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return aligned_tail;
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}
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/**
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* intel_dsb_commit() - Trigger workload execution of DSB.
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* @dsb: DSB context
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*
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* This function is used to do actual write to hardware using DSB.
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*/
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void intel_dsb_commit(struct intel_dsb *dsb)
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{
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struct intel_crtc *crtc = dsb->crtc;
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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u32 tail;
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tail = intel_dsb_align_tail(dsb);
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if (tail == 0)
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return;
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if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
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drm_err(&dev_priv->drm, "DSB engine is busy.\n");
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goto reset;
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}
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intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
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DSB_ENABLE);
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intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
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i915_ggtt_offset(dsb->vma));
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intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
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i915_ggtt_offset(dsb->vma) + tail);
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drm_dbg_kms(&dev_priv->drm,
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"DSB execution started - head 0x%x, tail 0x%x\n",
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i915_ggtt_offset(dsb->vma),
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i915_ggtt_offset(dsb->vma) + tail);
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if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
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drm_err(&dev_priv->drm,
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"Timed out waiting for DSB workload completion.\n");
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reset:
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dsb->free_pos = 0;
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dsb->ins_start_offset = 0;
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intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
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}
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/**
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* intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
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* @crtc: the CRTC
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* @max_cmds: number of commands we need to fit into command buffer
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*
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* This function prepare the command buffer which is used to store dsb
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* instructions with data.
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*
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* Returns:
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* DSB context, NULL on failure
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*/
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struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
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unsigned int max_cmds)
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{
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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struct drm_i915_gem_object *obj;
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intel_wakeref_t wakeref;
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struct intel_dsb *dsb;
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struct i915_vma *vma;
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unsigned int size;
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u32 *buf;
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if (!HAS_DSB(i915))
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return NULL;
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dsb = kzalloc(sizeof(*dsb), GFP_KERNEL);
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if (!dsb)
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goto out;
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wakeref = intel_runtime_pm_get(&i915->runtime_pm);
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/* ~1 qword per instruction, full cachelines */
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size = ALIGN(max_cmds * 8, CACHELINE_BYTES);
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obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size));
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if (IS_ERR(obj))
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goto out_put_rpm;
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
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if (IS_ERR(vma)) {
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i915_gem_object_put(obj);
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goto out_put_rpm;
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}
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buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
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if (IS_ERR(buf)) {
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i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP);
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goto out_put_rpm;
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}
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intel_runtime_pm_put(&i915->runtime_pm, wakeref);
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dsb->id = DSB1;
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dsb->vma = vma;
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dsb->crtc = crtc;
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dsb->cmd_buf = buf;
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dsb->size = size / 4; /* in dwords */
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dsb->free_pos = 0;
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dsb->ins_start_offset = 0;
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return dsb;
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out_put_rpm:
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intel_runtime_pm_put(&i915->runtime_pm, wakeref);
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kfree(dsb);
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out:
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drm_info_once(&i915->drm,
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"DSB queue setup failed, will fallback to MMIO for display HW programming\n");
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return NULL;
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}
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/**
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* intel_dsb_cleanup() - To cleanup DSB context.
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* @dsb: DSB context
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*
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* This function cleanup the DSB context by unpinning and releasing
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* the VMA object associated with it.
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*/
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void intel_dsb_cleanup(struct intel_dsb *dsb)
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{
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i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
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kfree(dsb);
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}
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