303 lines
8.0 KiB
C
303 lines
8.0 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021 Intel Corporation
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*/
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/**
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* DOC: display pinning helpers
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*/
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#include "gem/i915_gem_domain.h"
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#include "gem/i915_gem_object.h"
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#include "i915_drv.h"
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#include "intel_display_types.h"
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#include "intel_dpt.h"
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#include "intel_fb.h"
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#include "intel_fb_pin.h"
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static struct i915_vma *
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intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
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const struct i915_gtt_view *view,
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bool uses_fence,
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unsigned long *out_flags,
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struct i915_address_space *vm)
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{
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struct drm_device *dev = fb->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct i915_gem_ww_ctx ww;
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struct i915_vma *vma;
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u32 alignment;
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int ret;
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/*
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* We are not syncing against the binding (and potential migrations)
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* below, so this vm must never be async.
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*/
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GEM_WARN_ON(vm->bind_async_flags);
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if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
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return ERR_PTR(-EINVAL);
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alignment = 4096 * 512;
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atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
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for_i915_gem_ww(&ww, ret, true) {
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ret = i915_gem_object_lock(obj, &ww);
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if (ret)
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continue;
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if (HAS_LMEM(dev_priv)) {
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unsigned int flags = obj->flags;
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/*
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* For this type of buffer we need to able to read from the CPU
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* the clear color value found in the buffer, hence we need to
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* ensure it is always in the mappable part of lmem, if this is
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* a small-bar device.
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*/
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if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
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flags &= ~I915_BO_ALLOC_GPU_ONLY;
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ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
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flags);
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if (ret)
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continue;
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}
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ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
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if (ret)
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continue;
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vma = i915_vma_instance(obj, vm, view);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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continue;
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}
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if (i915_vma_misplaced(vma, 0, alignment, 0)) {
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ret = i915_vma_unbind(vma);
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if (ret)
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continue;
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}
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ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL);
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if (ret)
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continue;
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}
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if (ret) {
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vma = ERR_PTR(ret);
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goto err;
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}
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vma->display_alignment = max(vma->display_alignment, alignment);
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i915_gem_object_flush_if_display(obj);
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i915_vma_get(vma);
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err:
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atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
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return vma;
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}
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struct i915_vma *
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intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
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bool phys_cursor,
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const struct i915_gtt_view *view,
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bool uses_fence,
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unsigned long *out_flags)
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{
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struct drm_device *dev = fb->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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intel_wakeref_t wakeref;
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struct i915_gem_ww_ctx ww;
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struct i915_vma *vma;
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unsigned int pinctl;
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u32 alignment;
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int ret;
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if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
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return ERR_PTR(-EINVAL);
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if (phys_cursor)
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alignment = intel_cursor_alignment(dev_priv);
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else
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alignment = intel_surf_alignment(fb, 0);
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if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
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return ERR_PTR(-EINVAL);
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/* Note that the w/a also requires 64 PTE of padding following the
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* bo. We currently fill all unused PTE with the shadow page and so
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* we should always have valid PTE following the scanout preventing
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* the VT-d warning.
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*/
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if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
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alignment = 256 * 1024;
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/*
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* Global gtt pte registers are special registers which actually forward
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* writes to a chunk of system memory. Which means that there is no risk
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* that the register values disappear as soon as we call
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* intel_runtime_pm_put(), so it is correct to wrap only the
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* pin/unpin/fence and not more.
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*/
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wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
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atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
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/*
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* Valleyview is definitely limited to scanning out the first
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* 512MiB. Lets presume this behaviour was inherited from the
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* g4x display engine and that all earlier gen are similarly
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* limited. Testing suggests that it is a little more
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* complicated than this. For example, Cherryview appears quite
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* happy to scanout from anywhere within its global aperture.
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*/
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pinctl = 0;
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if (HAS_GMCH(dev_priv))
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pinctl |= PIN_MAPPABLE;
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i915_gem_ww_ctx_init(&ww, true);
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retry:
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ret = i915_gem_object_lock(obj, &ww);
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if (!ret && phys_cursor)
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ret = i915_gem_object_attach_phys(obj, alignment);
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else if (!ret && HAS_LMEM(dev_priv))
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ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
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if (!ret)
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ret = i915_gem_object_pin_pages(obj);
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if (ret)
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goto err;
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vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
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view, pinctl);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unpin;
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}
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if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
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/*
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* Install a fence for tiled scan-out. Pre-i965 always needs a
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* fence, whereas 965+ only requires a fence if using
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* framebuffer compression. For simplicity, we always, when
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* possible, install a fence as the cost is not that onerous.
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*
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* If we fail to fence the tiled scanout, then either the
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* modeset will reject the change (which is highly unlikely as
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* the affected systems, all but one, do not have unmappable
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* space) or we will not be able to enable full powersaving
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* techniques (also likely not to apply due to various limits
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* FBC and the like impose on the size of the buffer, which
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* presumably we violated anyway with this unmappable buffer).
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* Anyway, it is presumably better to stumble onwards with
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* something and try to run the system in a "less than optimal"
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* mode that matches the user configuration.
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*/
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ret = i915_vma_pin_fence(vma);
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if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
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i915_vma_unpin(vma);
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goto err_unpin;
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}
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ret = 0;
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if (vma->fence)
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*out_flags |= PLANE_HAS_FENCE;
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}
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i915_vma_get(vma);
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err_unpin:
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i915_gem_object_unpin_pages(obj);
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err:
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if (ret == -EDEADLK) {
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ret = i915_gem_ww_ctx_backoff(&ww);
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if (!ret)
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goto retry;
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}
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i915_gem_ww_ctx_fini(&ww);
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if (ret)
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vma = ERR_PTR(ret);
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atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
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intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
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return vma;
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}
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void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
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{
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if (flags & PLANE_HAS_FENCE)
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i915_vma_unpin_fence(vma);
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i915_vma_unpin(vma);
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i915_vma_put(vma);
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}
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int intel_plane_pin_fb(struct intel_plane_state *plane_state)
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{
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struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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struct drm_framebuffer *fb = plane_state->hw.fb;
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struct i915_vma *vma;
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bool phys_cursor =
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plane->id == PLANE_CURSOR &&
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INTEL_INFO(dev_priv)->display.cursor_needs_physical;
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if (!intel_fb_uses_dpt(fb)) {
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vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
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&plane_state->view.gtt,
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intel_plane_uses_fence(plane_state),
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&plane_state->flags);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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plane_state->ggtt_vma = vma;
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} else {
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struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
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vma = intel_dpt_pin(intel_fb->dpt_vm);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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plane_state->ggtt_vma = vma;
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vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
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&plane_state->flags, intel_fb->dpt_vm);
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if (IS_ERR(vma)) {
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intel_dpt_unpin(intel_fb->dpt_vm);
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plane_state->ggtt_vma = NULL;
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return PTR_ERR(vma);
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}
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plane_state->dpt_vma = vma;
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WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
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}
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return 0;
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}
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void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
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{
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struct drm_framebuffer *fb = old_plane_state->hw.fb;
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struct i915_vma *vma;
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if (!intel_fb_uses_dpt(fb)) {
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vma = fetch_and_zero(&old_plane_state->ggtt_vma);
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if (vma)
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intel_unpin_fb_vma(vma, old_plane_state->flags);
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} else {
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struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
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vma = fetch_and_zero(&old_plane_state->dpt_vma);
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if (vma)
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intel_unpin_fb_vma(vma, old_plane_state->flags);
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vma = fetch_and_zero(&old_plane_state->ggtt_vma);
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if (vma)
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intel_dpt_unpin(intel_fb->dpt_vm);
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}
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}
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