360 lines
12 KiB
C
360 lines
12 KiB
C
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/* SPDX-License-Identifier: MIT */
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#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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#include <asm/cacheflush.h>
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#include <drm/drm_util.h>
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#include <drm/drm_cache.h>
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#include <linux/hashtable.h>
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#include <linux/irq_work.h>
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#include <linux/random.h>
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#include <linux/seqlock.h>
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#include "i915_pmu.h"
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#include "i915_request.h"
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#include "i915_selftest.h"
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#include "intel_engine_types.h"
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#include "intel_gt_types.h"
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#include "intel_timeline.h"
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#include "intel_workarounds.h"
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struct drm_printer;
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struct intel_context;
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struct intel_gt;
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struct lock_class_key;
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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* but keeps the logic simple. Indeed, the whole purpose of this macro is just
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* to give some inclination as to some of the magic values used in the various
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* workarounds!
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*/
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#define CACHELINE_BYTES 64
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#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
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#define ENGINE_TRACE(e, fmt, ...) do { \
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const struct intel_engine_cs *e__ __maybe_unused = (e); \
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GEM_TRACE("%s %s: " fmt, \
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dev_name(e__->i915->drm.dev), e__->name, \
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##__VA_ARGS__); \
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} while (0)
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/*
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* The register defines to be used with the following macros need to accept a
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* base param, e.g:
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*
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* REG_FOO(base) _MMIO((base) + <relative offset>)
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* ENGINE_READ(engine, REG_FOO);
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*
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* register arrays are to be defined and accessed as follows:
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*
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* REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
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* ENGINE_READ_IDX(engine, REG_BAR, i)
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*/
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#define __ENGINE_REG_OP(op__, engine__, ...) \
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intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
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#define __ENGINE_READ_OP(op__, engine__, reg__) \
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__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
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#define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__)
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#define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
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#define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
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#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
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#define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
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#define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
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__ENGINE_REG_OP(read64_2x32, (engine__), \
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lower_reg__((engine__)->mmio_base), \
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upper_reg__((engine__)->mmio_base))
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#define ENGINE_READ_IDX(engine__, reg__, idx__) \
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__ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
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#define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
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__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
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#define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__)
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#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
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#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
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#define GEN6_RING_FAULT_REG_READ(engine__) \
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intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
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#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
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intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
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#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
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({ \
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u32 __val; \
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\
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__val = intel_uncore_read((engine__)->uncore, \
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RING_FAULT_REG(engine__)); \
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__val &= ~(clear__); \
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__val |= (set__); \
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intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
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__val); \
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})
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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static inline unsigned int
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execlists_num_ports(const struct intel_engine_execlists * const execlists)
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{
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return execlists->port_mask + 1;
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}
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static inline struct i915_request *
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execlists_active(const struct intel_engine_execlists *execlists)
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{
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struct i915_request * const *cur, * const *old, *active;
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cur = READ_ONCE(execlists->active);
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smp_rmb(); /* pairs with overwrite protection in process_csb() */
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do {
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old = cur;
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active = READ_ONCE(*cur);
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cur = READ_ONCE(execlists->active);
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smp_rmb(); /* and complete the seqlock retry */
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} while (unlikely(cur != old));
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return active;
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}
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struct i915_request *
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execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
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static inline u32
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intel_read_status_page(const struct intel_engine_cs *engine, int reg)
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{
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/* Ensure that the compiler doesn't optimize away the load. */
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return READ_ONCE(engine->status_page.addr[reg]);
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}
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static inline void
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intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
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{
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/* Writing into the status page should be done sparingly. Since
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* we do when we are uncertain of the device state, we take a bit
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* of extra paranoia to try and ensure that the HWS takes the value
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* we give and that it doesn't end up trapped inside the CPU!
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*/
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drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
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WRITE_ONCE(engine->status_page.addr[reg], value);
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drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
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}
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/*
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* Reads a dword out of the status page, which is written to from the command
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* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
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* MI_STORE_DATA_IMM.
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*
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* The following dwords have a reserved meaning:
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* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
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* 0x04: ring 0 head pointer
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* 0x05: ring 1 head pointer (915-class)
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* 0x06: ring 2 head pointer (915-class)
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* 0x10-0x1b: Context status DWords (GM45)
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* 0x1f: Last written status offset. (GM45)
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* 0x20-0x2f: Reserved (Gen6+)
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*
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* The area from dword 0x30 to 0x3ff is available for driver usage.
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*/
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#define I915_GEM_HWS_PREEMPT 0x32
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#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
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#define I915_GEM_HWS_SEQNO 0x40
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#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
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#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
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#define I915_GEM_HWS_PXP 0x60
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#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
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#define I915_GEM_HWS_GSC 0x62
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#define I915_GEM_HWS_GSC_ADDR (I915_GEM_HWS_GSC * sizeof(u32))
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#define I915_GEM_HWS_SCRATCH 0x80
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#define I915_HWS_CSB_BUF0_INDEX 0x10
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#define I915_HWS_CSB_WRITE_INDEX 0x1f
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#define ICL_HWS_CSB_WRITE_INDEX 0x2f
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#define INTEL_HWS_CSB_WRITE_INDEX(__i915) \
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(GRAPHICS_VER(__i915) >= 11 ? ICL_HWS_CSB_WRITE_INDEX : I915_HWS_CSB_WRITE_INDEX)
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void intel_engine_stop(struct intel_engine_cs *engine);
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void intel_engine_cleanup(struct intel_engine_cs *engine);
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int intel_engines_init_mmio(struct intel_gt *gt);
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int intel_engines_init(struct intel_gt *gt);
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void intel_engine_free_request_pool(struct intel_engine_cs *engine);
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void intel_engines_release(struct intel_gt *gt);
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void intel_engines_free(struct intel_gt *gt);
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int intel_engine_init_common(struct intel_engine_cs *engine);
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void intel_engine_cleanup_common(struct intel_engine_cs *engine);
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int intel_engine_resume(struct intel_engine_cs *engine);
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int intel_ring_submission_setup(struct intel_engine_cs *engine);
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int intel_engine_stop_cs(struct intel_engine_cs *engine);
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void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
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void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
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void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
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u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
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u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
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void intel_engine_get_instdone(const struct intel_engine_cs *engine,
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struct intel_instdone *instdone);
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void intel_engine_init_execlists(struct intel_engine_cs *engine);
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bool intel_engine_irq_enable(struct intel_engine_cs *engine);
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void intel_engine_irq_disable(struct intel_engine_cs *engine);
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static inline void __intel_engine_reset(struct intel_engine_cs *engine,
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bool stalled)
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{
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if (engine->reset.rewind)
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engine->reset.rewind(engine, stalled);
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engine->serial++; /* contexts lost */
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}
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bool intel_engines_are_idle(struct intel_gt *gt);
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bool intel_engine_is_idle(struct intel_engine_cs *engine);
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void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);
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static inline void intel_engine_flush_submission(struct intel_engine_cs *engine)
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{
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__intel_engine_flush_submission(engine, true);
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}
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void intel_engines_reset_default_submission(struct intel_gt *gt);
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bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
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__printf(3, 4)
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void intel_engine_dump(struct intel_engine_cs *engine,
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struct drm_printer *m,
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const char *header, ...);
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void intel_engine_dump_active_requests(struct list_head *requests,
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struct i915_request *hung_rq,
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struct drm_printer *m);
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ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,
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ktime_t *now);
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void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
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struct intel_context **ce, struct i915_request **rq);
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u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
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struct intel_context *
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intel_engine_create_pinned_context(struct intel_engine_cs *engine,
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struct i915_address_space *vm,
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unsigned int ring_size,
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unsigned int hwsp,
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struct lock_class_key *key,
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const char *name);
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void intel_engine_destroy_pinned_context(struct intel_context *ce);
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void xehp_enable_ccs_engines(struct intel_engine_cs *engine);
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#define ENGINE_PHYSICAL 0
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#define ENGINE_MOCK 1
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#define ENGINE_VIRTUAL 2
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static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
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{
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return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
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}
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static inline bool
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intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
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{
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if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT)
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return false;
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return intel_engine_has_preemption(engine);
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}
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#define FORCE_VIRTUAL BIT(0)
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struct intel_context *
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intel_engine_create_virtual(struct intel_engine_cs **siblings,
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unsigned int count, unsigned long flags);
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static inline struct intel_context *
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intel_engine_create_parallel(struct intel_engine_cs **engines,
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unsigned int num_engines,
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unsigned int width)
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{
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GEM_BUG_ON(!engines[0]->cops->create_parallel);
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return engines[0]->cops->create_parallel(engines, num_engines, width);
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}
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static inline bool
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intel_virtual_engine_has_heartbeat(const struct intel_engine_cs *engine)
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{
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/*
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* For non-GuC submission we expect the back-end to look at the
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* heartbeat status of the actual physical engine that the work
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* has been (or is being) scheduled on, so we should only reach
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* here with GuC submission enabled.
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*/
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GEM_BUG_ON(!intel_engine_uses_guc(engine));
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return intel_guc_virtual_engine_has_heartbeat(engine);
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}
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static inline bool
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intel_engine_has_heartbeat(const struct intel_engine_cs *engine)
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{
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if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
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return false;
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if (intel_engine_is_virtual(engine))
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return intel_virtual_engine_has_heartbeat(engine);
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else
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return READ_ONCE(engine->props.heartbeat_interval_ms);
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}
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static inline struct intel_engine_cs *
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intel_engine_get_sibling(struct intel_engine_cs *engine, unsigned int sibling)
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{
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GEM_BUG_ON(!intel_engine_is_virtual(engine));
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return engine->cops->get_sibling(engine, sibling);
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}
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static inline void
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intel_engine_set_hung_context(struct intel_engine_cs *engine,
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struct intel_context *ce)
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{
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engine->hung_ce = ce;
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}
|
||
|
|
|
||
|
|
static inline void
|
||
|
|
intel_engine_clear_hung_context(struct intel_engine_cs *engine)
|
||
|
|
{
|
||
|
|
intel_engine_set_hung_context(engine, NULL);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct intel_context *
|
||
|
|
intel_engine_get_hung_context(struct intel_engine_cs *engine)
|
||
|
|
{
|
||
|
|
return engine->hung_ce;
|
||
|
|
}
|
||
|
|
|
||
|
|
u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value);
|
||
|
|
u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value);
|
||
|
|
u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value);
|
||
|
|
u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);
|
||
|
|
u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);
|
||
|
|
|
||
|
|
#endif /* _INTEL_RINGBUFFER_H_ */
|