208 lines
6.1 KiB
C
208 lines
6.1 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2014-2019 Intel Corporation
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*
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* Authors:
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* Vinit Azad <vinit.azad@intel.com>
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* Ben Widawsky <ben@bwidawsk.net>
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* Dave Gordon <david.s.gordon@intel.com>
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* Alex Dai <yu.dai@intel.com>
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*/
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_mcr.h"
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#include "gt/intel_gt_regs.h"
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#include "intel_guc_fw.h"
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#include "intel_guc_print.h"
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#include "i915_drv.h"
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static void guc_prepare_xfer(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
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GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
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GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
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GUC_ENABLE_MIA_CLOCK_GATING;
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if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
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shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
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GUC_ENABLE_MIA_CACHING;
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/* Must program this register before loading the ucode with DMA */
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intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
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if (IS_GEN9_LP(uncore->i915))
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intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
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else
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intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
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if (GRAPHICS_VER(uncore->i915) == 9) {
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/* DOP Clock Gating Enable for GuC clocks */
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intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0,
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GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
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/* allows for 5us (in 10ns units) before GT can go to RC6 */
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intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
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}
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}
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static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw,
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struct intel_uncore *uncore)
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{
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u32 rsa[UOS_RSA_SCRATCH_COUNT];
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size_t copied;
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int i;
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copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
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if (copied < sizeof(rsa))
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return -ENOMEM;
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for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
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intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
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return 0;
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}
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static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw,
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struct intel_uncore *uncore)
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{
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struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
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intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
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intel_guc_ggtt_offset(guc, guc_fw->rsa_data));
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return 0;
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}
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/* Copy RSA signature from the fw image to HW for verification */
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static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
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struct intel_uncore *uncore)
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{
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if (guc_fw->rsa_data)
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return guc_xfer_rsa_vma(guc_fw, uncore);
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else
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return guc_xfer_rsa_mmio(guc_fw, uncore);
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}
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/*
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* Read the GuC status register (GUC_STATUS) and store it in the
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* specified location; then return a boolean indicating whether
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* the value matches either of two values representing completion
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* of the GuC boot process.
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*
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* This is used for polling the GuC status in a wait_for()
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* loop below.
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*/
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static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
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{
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u32 val = intel_uncore_read(uncore, GUC_STATUS);
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u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
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*status = val;
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return uk_val == INTEL_GUC_LOAD_STATUS_READY;
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}
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static int guc_wait_ucode(struct intel_guc *guc)
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{
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struct intel_gt *gt = guc_to_gt(guc);
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struct intel_uncore *uncore = gt->uncore;
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u32 status;
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int ret;
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/*
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* Wait for the GuC to start up.
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* NB: Docs recommend not using the interrupt for completion.
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* Measurements indicate this should take no more than 20ms
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* (assuming the GT clock is at maximum frequency). So, a
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* timeout here indicates that the GuC has failed and is unusable.
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* (Higher levels of the driver may decide to reset the GuC and
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* attempt the ucode load again if this happens.)
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*
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* FIXME: There is a known (but exceedingly unlikely) race condition
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* where the asynchronous frequency management code could reduce
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* the GT clock while a GuC reload is in progress (during a full
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* GT reset). A fix is in progress but there are complex locking
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* issues to be resolved. In the meantime bump the timeout to
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* 200ms. Even at slowest clock, this should be sufficient. And
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* in the working case, a larger timeout makes no difference.
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*/
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ret = wait_for(guc_ready(uncore, &status), 200);
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if (ret) {
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guc_info(guc, "load failed: status = 0x%08X\n", status);
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guc_info(guc, "load failed: status: Reset = %d, "
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"BootROM = 0x%02X, UKernel = 0x%02X, "
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"MIA = 0x%02X, Auth = 0x%02X\n",
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REG_FIELD_GET(GS_MIA_IN_RESET, status),
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REG_FIELD_GET(GS_BOOTROM_MASK, status),
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REG_FIELD_GET(GS_UKERNEL_MASK, status),
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REG_FIELD_GET(GS_MIA_MASK, status),
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REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
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if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
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guc_info(guc, "firmware signature verification failed\n");
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ret = -ENOEXEC;
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}
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if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
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guc_info(guc, "firmware exception. EIP: %#x\n",
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intel_uncore_read(uncore, SOFT_SCRATCH(13)));
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ret = -ENXIO;
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}
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}
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return ret;
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}
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/**
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* intel_guc_fw_upload() - load GuC uCode to device
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* @guc: intel_guc structure
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*
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* Called from intel_uc_init_hw() during driver load, resume from sleep and
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* after a GPU reset.
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*
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* The firmware image should have already been fetched into memory, so only
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* check that fetch succeeded, and then transfer the image to the h/w.
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*
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* Return: non-zero code on error
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*/
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int intel_guc_fw_upload(struct intel_guc *guc)
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{
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struct intel_gt *gt = guc_to_gt(guc);
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struct intel_uncore *uncore = gt->uncore;
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int ret;
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guc_prepare_xfer(gt);
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/*
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* Note that GuC needs the CSS header plus uKernel code to be copied
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* by the DMA engine in one operation, whereas the RSA signature is
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* loaded separately, either by copying it to the UOS_RSA_SCRATCH
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* register (if key size <= 256) or through a ggtt-pinned vma (if key
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* size > 256). The RSA size and therefore the way we provide it to the
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* HW is fixed for each platform and hard-coded in the bootrom.
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*/
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ret = guc_xfer_rsa(&guc->fw, uncore);
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if (ret)
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goto out;
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/*
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* Current uCode expects the code to be loaded at 8k; locations below
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* this are used for the stack.
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*/
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ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
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if (ret)
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goto out;
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ret = guc_wait_ucode(guc);
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if (ret)
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goto out;
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intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
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return 0;
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out:
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intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
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return ret;
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}
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